traffic_controller.tan.qmsg

实现交通灯控制器的vhdl编程

{ "Info" "ITDB_FULL_TCO_RESULT" "clk50M YELLOWB controller:inst\|yellowB 14.364 ns register " "Info: tco from clock \"clk50M\" to destination pin \"YELLOWB\" through register \"controller:inst\|yellowB\" is 14.364 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M source 7.685 ns + Longest register " "Info: + Longest clock path from clock \"clk50M\" to source register is 7.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns frequency20Hz:inst3\|clk 3 REG LCFF_X1_Y18_N21 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 2; REG Node = 'frequency20Hz:inst3\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk50M~clkctrl frequency20Hz:inst3|clk } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 3.553 ns frequency20Hz:inst3\|clk~clkctrl 4 COMB CLKCTRL_G3 35 " "Info: 4: + IC(0.626 ns) + CELL(0.000 ns) = 3.553 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'frequency20Hz:inst3\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.626 ns" { frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.787 ns) 5.367 ns frequency1Hz:inst2\|clk 5 REG LCFF_X34_Y1_N21 2 " "Info: 5: + IC(1.027 ns) + CELL(0.787 ns) = 5.367 ns; Loc. = LCFF_X34_Y1_N21; Fanout = 2; REG Node = 'frequency1Hz:inst2\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.814 ns" { frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.000 ns) 6.102 ns frequency1Hz:inst2\|clk~clkctrl 6 COMB CLKCTRL_G15 23 " "Info: 6: + IC(0.735 ns) + CELL(0.000 ns) = 6.102 ns; Loc. = CLKCTRL_G15; Fanout = 23; COMB Node = 'frequency1Hz:inst2\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.735 ns" { frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.537 ns) 7.685 ns controller:inst\|yellowB 7 REG LCFF_X31_Y16_N23 1 " "Info: 7: + IC(1.046 ns) + CELL(0.537 ns) = 7.685 ns; Loc. = LCFF_X31_Y16_N23; Fanout = 1; REG Node = 'controller:inst\|yellowB'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.583 ns" { frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 40.47 % ) " "Info: Total cell delay = 3.110 ns ( 40.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.575 ns ( 59.53 % ) " "Info: Total interconnect delay = 4.575 ns ( 59.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.685 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.685 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.046ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.429 ns + Longest register pin " "Info: + Longest register to pin delay is 6.429 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns controller:inst\|yellowB 1 REG LCFF_X31_Y16_N23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y16_N23; Fanout = 1; REG Node = 'controller:inst\|yellowB'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { controller:inst|yellowB } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.611 ns) + CELL(2.818 ns) 6.429 ns YELLOWB 2 PIN PIN_AF23 0 " "Info: 2: + IC(3.611 ns) + CELL(2.818 ns) = 6.429 ns; Loc. = PIN_AF23; Fanout = 0; PIN Node = 'YELLOWB'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.429 ns" { controller:inst|yellowB YELLOWB } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 224 856 1032 240 "YELLOWB" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.818 ns ( 43.83 % ) " "Info: Total cell delay = 2.818 ns ( 43.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.611 ns ( 56.17 % ) " "Info: Total interconnect delay = 3.611 ns ( 56.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.429 ns" { controller:inst|yellowB YELLOWB } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.429 ns" { controller:inst|yellowB YELLOWB } { 0.000ns 3.611ns } { 0.000ns 2.818ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.685 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.685 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.046ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.429 ns" { controller:inst|yellowB YELLOWB } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.429 ns" { controller:inst|yellowB YELLOWB } { 0.000ns 3.611ns } { 0.000ns 2.818ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "controller:inst\|yellowB hold clk50M 5.002 ns register " "Info: th for register \"controller:inst\|yellowB\" (data pin = \"hold\", clock pin = \"clk50M\") is 5.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M destination 7.685 ns + Longest register " "Info: + Longest clock path from clock \"clk50M\" to destination register is 7.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns frequency20Hz:inst3\|clk 3 REG LCFF_X1_Y18_N21 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 2; REG Node = 'frequency20Hz:inst3\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk50M~clkctrl frequency20Hz:inst3|clk } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 3.553 ns frequency20Hz:inst3\|clk~clkctrl 4 COMB CLKCTRL_G3 35 " "Info: 4: + IC(0.626 ns) + CELL(0.000 ns) = 3.553 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'frequency20Hz:inst3\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.626 ns" { frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.787 ns) 5.367 ns frequency1Hz:inst2\|clk 5 REG LCFF_X34_Y1_N21 2 " "Info: 5: + IC(1.027 ns) + CELL(0.787 ns) = 5.367 ns; Loc. = LCFF_X34_Y1_N21; Fanout = 2; REG Node = 'frequency1Hz:inst2\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.814 ns" { frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.000 ns) 6.102 ns frequency1Hz:inst2\|clk~clkctrl 6 COMB CLKCTRL_G15 23 " "Info: 6: + IC(0.735 ns) + CELL(0.000 ns) = 6.102 ns; Loc. = CLKCTRL_G15; Fanout = 23; COMB Node = 'frequency1Hz:inst2\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.735 ns" { frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.537 ns) 7.685 ns controller:inst\|yellowB 7 REG LCFF_X31_Y16_N23 1 " "Info: 7: + IC(1.046 ns) + CELL(0.537 ns) = 7.685 ns; Loc. = LCFF_X31_Y16_N23; Fanout = 1; REG Node = 'controller:inst\|yellowB'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.583 ns" { frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 40.47 % ) " "Info: Total cell delay = 3.110 ns ( 40.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.575 ns ( 59.53 % ) " "Info: Total interconnect delay = 4.575 ns ( 59.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.685 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.685 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.046ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.949 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns hold 1 PIN PIN_N26 23 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 23; PIN Node = 'hold'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hold } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 40 360 528 56 "hold" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.591 ns) + CELL(0.275 ns) 2.865 ns controller:inst\|yellowB~28 2 COMB LCCOMB_X31_Y16_N22 1 " "Info: 2: + IC(1.591 ns) + CELL(0.275 ns) = 2.865 ns; Loc. = LCCOMB_X31_Y16_N22; Fanout = 1; COMB Node = 'controller:inst\|yellowB~28'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.866 ns" { hold controller:inst|yellowB~28 } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.949 ns controller:inst\|yellowB 3 REG LCFF_X31_Y16_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.949 ns; Loc. = LCFF_X31_Y16_N23; Fanout = 1; REG Node = 'controller:inst\|yellowB'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { controller:inst|yellowB~28 controller:inst|yellowB } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.358 ns ( 46.05 % ) " "Info: Total cell delay = 1.358 ns ( 46.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.591 ns ( 53.95 % ) " "Info: Total interconnect delay = 1.591 ns ( 53.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.949 ns" { hold controller:inst|yellowB~28 controller:inst|yellowB } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.949 ns" { hold hold~combout controller:inst|yellowB~28 controller:inst|yellowB } { 0.000ns 0.000ns 1.591ns 0.000ns } { 0.000ns 0.999ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.685 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.685 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|yellowB } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.046ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns