traffic_controller.tan.qmsg

实现交通灯控制器的vhdl编程

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk50M 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk50M\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "fenwei:inst5\|numA\[1\] display:inst7\|display\[6\] clk50M 98 ps " "Info: Found hold time violation between source  pin or register \"fenwei:inst5\|numA\[1\]\" and destination pin or register \"display:inst7\|display\[6\]\" for clock \"clk50M\" (Hold time is 98 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.425 ns + Largest " "Info: + Largest clock skew is 2.425 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M destination 5.118 ns + Longest register " "Info: + Longest clock path from clock \"clk50M\" to destination register is 5.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns frequency20Hz:inst3\|clk 3 REG LCFF_X1_Y18_N21 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 2; REG Node = 'frequency20Hz:inst3\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk50M~clkctrl frequency20Hz:inst3|clk } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 3.553 ns frequency20Hz:inst3\|clk~clkctrl 4 COMB CLKCTRL_G3 35 " "Info: 4: + IC(0.626 ns) + CELL(0.000 ns) = 3.553 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'frequency20Hz:inst3\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.626 ns" { frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 5.118 ns display:inst7\|display\[6\] 5 REG LCFF_X4_Y17_N29 1 " "Info: 5: + IC(1.028 ns) + CELL(0.537 ns) = 5.118 ns; Loc. = LCFF_X4_Y17_N29; Fanout = 1; REG Node = 'display:inst7\|display\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.565 ns" { frequency20Hz:inst3|clk~clkctrl display:inst7|display[6] } "NODE_NAME" } } { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.39 % ) " "Info: Total cell delay = 2.323 ns ( 45.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.795 ns ( 54.61 % ) " "Info: Total interconnect delay = 2.795 ns ( 54.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.118 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl display:inst7|display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.118 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl display:inst7|display[6] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M source 2.693 ns - Shortest register " "Info: - Shortest clock path from clock \"clk50M\" to source register is 2.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.537 ns) 2.693 ns fenwei:inst5\|numA\[1\] 3 REG LCFF_X30_Y16_N7 4 " "Info: 3: + IC(1.039 ns) + CELL(0.537 ns) = 2.693 ns; Loc. = LCFF_X30_Y16_N7; Fanout = 4; REG Node = 'fenwei:inst5\|numA\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.576 ns" { clk50M~clkctrl fenwei:inst5|numA[1] } "NODE_NAME" } } { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.04 % ) " "Info: Total cell delay = 1.536 ns ( 57.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.157 ns ( 42.96 % ) " "Info: Total interconnect delay = 1.157 ns ( 42.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { clk50M clk50M~clkctrl fenwei:inst5|numA[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { clk50M clk50M~combout clk50M~clkctrl fenwei:inst5|numA[1] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.118 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl display:inst7|display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.118 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl display:inst7|display[6] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { clk50M clk50M~clkctrl fenwei:inst5|numA[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { clk50M clk50M~combout clk50M~clkctrl fenwei:inst5|numA[1] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.343 ns - Shortest register register " "Info: - Shortest register to register delay is 2.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenwei:inst5\|numA\[1\] 1 REG LCFF_X30_Y16_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y16_N7; Fanout = 4; REG Node = 'fenwei:inst5\|numA\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fenwei:inst5|numA[1] } "NODE_NAME" } } { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.109 ns) + CELL(0.150 ns) 2.259 ns display:inst7\|display~57 2 COMB LCCOMB_X4_Y17_N28 1 " "Info: 2: + IC(2.109 ns) + CELL(0.150 ns) = 2.259 ns; Loc. = LCCOMB_X4_Y17_N28; Fanout = 1; COMB Node = 'display:inst7\|display~57'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.259 ns" { fenwei:inst5|numA[1] display:inst7|display~57 } "NODE_NAME" } } { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.343 ns display:inst7\|display\[6\] 3 REG LCFF_X4_Y17_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.343 ns; Loc. = LCFF_X4_Y17_N29; Fanout = 1; REG Node = 'display:inst7\|display\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { display:inst7|display~57 display:inst7|display[6] } "NODE_NAME" } } { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 9.99 % ) " "Info: Total cell delay = 0.234 ns ( 9.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.109 ns ( 90.01 % ) " "Info: Total interconnect delay = 2.109 ns ( 90.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.343 ns" { fenwei:inst5|numA[1] display:inst7|display~57 display:inst7|display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.343 ns" { fenwei:inst5|numA[1] display:inst7|display~57 display:inst7|display[6] } { 0.000ns 2.109ns 0.000ns } { 0.000ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.118 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl display:inst7|display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.118 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl display:inst7|display[6] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { clk50M clk50M~clkctrl fenwei:inst5|numA[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { clk50M clk50M~combout clk50M~clkctrl fenwei:inst5|numA[1] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.343 ns" { fenwei:inst5|numA[1] display:inst7|display~57 display:inst7|display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.343 ns" { fenwei:inst5|numA[1] display:inst7|display~57 display:inst7|display[6] } { 0.000ns 2.109ns 0.000ns } { 0.000ns 0.150ns 0.084ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "controller:inst\|flash reset clk50M -3.965 ns register " "Info: tsu for register \"controller:inst\|flash\" (data pin = \"reset\", clock pin = \"clk50M\") is -3.965 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.744 ns + Longest pin register " "Info: + Longest pin to register delay is 3.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns reset 1 PIN PIN_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 8 376 544 24 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.223 ns) + CELL(0.438 ns) 3.660 ns controller:inst\|flash~7 2 COMB LCCOMB_X4_Y17_N6 1 " "Info: 2: + IC(2.223 ns) + CELL(0.438 ns) = 3.660 ns; Loc. = LCCOMB_X4_Y17_N6; Fanout = 1; COMB Node = 'controller:inst\|flash~7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.661 ns" { reset controller:inst|flash~7 } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.744 ns controller:inst\|flash 3 REG LCFF_X4_Y17_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.744 ns; Loc. = LCFF_X4_Y17_N7; Fanout = 2; REG Node = 'controller:inst\|flash'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { controller:inst|flash~7 controller:inst|flash } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.521 ns ( 40.63 % ) " "Info: Total cell delay = 1.521 ns ( 40.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.223 ns ( 59.38 % ) " "Info: Total interconnect delay = 2.223 ns ( 59.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.744 ns" { reset controller:inst|flash~7 controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.744 ns" { reset reset~combout controller:inst|flash~7 controller:inst|flash } { 0.000ns 0.000ns 2.223ns 0.000ns } { 0.000ns 0.999ns 0.438ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M destination 7.673 ns - Shortest register " "Info: - Shortest clock path from clock \"clk50M\" to destination register is 7.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns frequency20Hz:inst3\|clk 3 REG LCFF_X1_Y18_N21 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 2; REG Node = 'frequency20Hz:inst3\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk50M~clkctrl frequency20Hz:inst3|clk } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 3.553 ns frequency20Hz:inst3\|clk~clkctrl 4 COMB CLKCTRL_G3 35 " "Info: 4: + IC(0.626 ns) + CELL(0.000 ns) = 3.553 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'frequency20Hz:inst3\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.626 ns" { frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.787 ns) 5.367 ns frequency1Hz:inst2\|clk 5 REG LCFF_X34_Y1_N21 2 " "Info: 5: + IC(1.027 ns) + CELL(0.787 ns) = 5.367 ns; Loc. = LCFF_X34_Y1_N21; Fanout = 2; REG Node = 'frequency1Hz:inst2\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.814 ns" { frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.000 ns) 6.102 ns frequency1Hz:inst2\|clk~clkctrl 6 COMB CLKCTRL_G15 23 " "Info: 6: + IC(0.735 ns) + CELL(0.000 ns) = 6.102 ns; Loc. = CLKCTRL_G15; Fanout = 23; COMB Node = 'frequency1Hz:inst2\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.735 ns" { frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.537 ns) 7.673 ns controller:inst\|flash 7 REG LCFF_X4_Y17_N7 2 " "Info: 7: + IC(1.034 ns) + CELL(0.537 ns) = 7.673 ns; Loc. = LCFF_X4_Y17_N7; Fanout = 2; REG Node = 'controller:inst\|flash'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.571 ns" { frequency1Hz:inst2|clk~clkctrl controller:inst|flash } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 40.53 % ) " "Info: Total cell delay = 3.110 ns ( 40.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.563 ns ( 59.47 % ) " "Info: Total interconnect delay = 4.563 ns ( 59.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.673 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.673 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|flash } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.744 ns" { reset controller:inst|flash~7 controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.744 ns" { reset reset~combout controller:inst|flash~7 controller:inst|flash } { 0.000ns 0.000ns 2.223ns 0.000ns } { 0.000ns 0.999ns 0.438ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.673 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|flash } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.673 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|flash } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}