📄 traffic_controller.tan.qmsg

📁 实现交通灯控制器的vhdl编程
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk50M " "Info: Assuming node \"clk50M\" is an undefined clock" {  } { { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk50M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "frequency20Hz:inst3\|clk " "Info: Detected ripple clock \"frequency20Hz:inst3\|clk\" as buffer" {  } { { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "frequency20Hz:inst3\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency1Hz:inst2\|clk " "Info: Detected ripple clock \"frequency1Hz:inst2\|clk\" as buffer" {  } { { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "frequency1Hz:inst2\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk50M register controller:inst\|numB\[2\] register fenwei:inst5\|numB\[1\] 163.88 MHz 6.102 ns Internal " "Info: Clock \"clk50M\" has Internal fmax of 163.88 MHz between source register \"controller:inst\|numB\[2\]\" and destination register \"fenwei:inst5\|numB\[1\]\" (period= 6.102 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.897 ns + Longest register register " "Info: + Longest register to register delay is 0.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns controller:inst\|numB\[2\] 1 REG LCFF_X30_Y16_N21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y16_N21; Fanout = 5; REG Node = 'controller:inst\|numB\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { controller:inst|numB[2] } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.437 ns) 0.813 ns fenwei:inst5\|numB~529 2 COMB LCCOMB_X30_Y16_N0 1 " "Info: 2: + IC(0.376 ns) + CELL(0.437 ns) = 0.813 ns; Loc. = LCCOMB_X30_Y16_N0; Fanout = 1; COMB Node = 'fenwei:inst5\|numB~529'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.813 ns" { controller:inst|numB[2] fenwei:inst5|numB~529 } "NODE_NAME" } } { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.897 ns fenwei:inst5\|numB\[1\] 3 REG LCFF_X30_Y16_N1 7 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.897 ns; Loc. = LCFF_X30_Y16_N1; Fanout = 7; REG Node = 'fenwei:inst5\|numB\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { fenwei:inst5|numB~529 fenwei:inst5|numB[1] } "NODE_NAME" } } { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.521 ns ( 58.08 % ) " "Info: Total cell delay = 0.521 ns ( 58.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.376 ns ( 41.92 % ) " "Info: Total interconnect delay = 0.376 ns ( 41.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.897 ns" { controller:inst|numB[2] fenwei:inst5|numB~529 fenwei:inst5|numB[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.897 ns" { controller:inst|numB[2] fenwei:inst5|numB~529 fenwei:inst5|numB[1] } { 0.000ns 0.376ns 0.000ns } { 0.000ns 0.437ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.991 ns - Smallest " "Info: - Smallest clock skew is -4.991 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M destination 2.693 ns + Shortest register " "Info: + Shortest clock path from clock \"clk50M\" to destination register is 2.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.537 ns) 2.693 ns fenwei:inst5\|numB\[1\] 3 REG LCFF_X30_Y16_N1 7 " "Info: 3: + IC(1.039 ns) + CELL(0.537 ns) = 2.693 ns; Loc. = LCFF_X30_Y16_N1; Fanout = 7; REG Node = 'fenwei:inst5\|numB\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.576 ns" { clk50M~clkctrl fenwei:inst5|numB[1] } "NODE_NAME" } } { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.04 % ) " "Info: Total cell delay = 1.536 ns ( 57.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.157 ns ( 42.96 % ) " "Info: Total interconnect delay = 1.157 ns ( 42.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { clk50M clk50M~clkctrl fenwei:inst5|numB[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { clk50M clk50M~combout clk50M~clkctrl fenwei:inst5|numB[1] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M source 7.684 ns - Longest register " "Info: - Longest clock path from clock \"clk50M\" to source register is 7.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 96 -24 144 112 "clk50M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns frequency20Hz:inst3\|clk 3 REG LCFF_X1_Y18_N21 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 2; REG Node = 'frequency20Hz:inst3\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk50M~clkctrl frequency20Hz:inst3|clk } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 3.553 ns frequency20Hz:inst3\|clk~clkctrl 4 COMB CLKCTRL_G3 35 " "Info: 4: + IC(0.626 ns) + CELL(0.000 ns) = 3.553 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'frequency20Hz:inst3\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.626 ns" { frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl } "NODE_NAME" } } { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.787 ns) 5.367 ns frequency1Hz:inst2\|clk 5 REG LCFF_X34_Y1_N21 2 " "Info: 5: + IC(1.027 ns) + CELL(0.787 ns) = 5.367 ns; Loc. = LCFF_X34_Y1_N21; Fanout = 2; REG Node = 'frequency1Hz:inst2\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.814 ns" { frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.000 ns) 6.102 ns frequency1Hz:inst2\|clk~clkctrl 6 COMB CLKCTRL_G15 23 " "Info: 6: + IC(0.735 ns) + CELL(0.000 ns) = 6.102 ns; Loc. = CLKCTRL_G15; Fanout = 23; COMB Node = 'frequency1Hz:inst2\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.735 ns" { frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl } "NODE_NAME" } } { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.537 ns) 7.684 ns controller:inst\|numB\[2\] 7 REG LCFF_X30_Y16_N21 5 " "Info: 7: + IC(1.045 ns) + CELL(0.537 ns) = 7.684 ns; Loc. = LCFF_X30_Y16_N21; Fanout = 5; REG Node = 'controller:inst\|numB\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.582 ns" { frequency1Hz:inst2|clk~clkctrl controller:inst|numB[2] } "NODE_NAME" } } { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 40.47 % ) " "Info: Total cell delay = 3.110 ns ( 40.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.574 ns ( 59.53 % ) " "Info: Total interconnect delay = 4.574 ns ( 59.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.684 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|numB[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.684 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|numB[2] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.045ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { clk50M clk50M~clkctrl fenwei:inst5|numB[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { clk50M clk50M~combout clk50M~clkctrl fenwei:inst5|numB[1] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.684 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|numB[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.684 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|numB[2] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.045ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.897 ns" { controller:inst|numB[2] fenwei:inst5|numB~529 fenwei:inst5|numB[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.897 ns" { controller:inst|numB[2] fenwei:inst5|numB~529 fenwei:inst5|numB[1] } { 0.000ns 0.376ns 0.000ns } { 0.000ns 0.437ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { clk50M clk50M~clkctrl fenwei:inst5|numB[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { clk50M clk50M~combout clk50M~clkctrl fenwei:inst5|numB[1] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.684 ns" { clk50M clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|numB[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.684 ns" { clk50M clk50M~combout clk50M~clkctrl frequency20Hz:inst3|clk frequency20Hz:inst3|clk~clkctrl frequency1Hz:inst2|clk frequency1Hz:inst2|clk~clkctrl controller:inst|numB[2] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.027ns 0.735ns 1.045ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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