traffic_controller.hier_info

实现交通灯控制器的vhdl编程

|traffic_controller
REDA <= controller:inst.redA
clk50M => frequency20Hz:inst3.clk50M
clk50M => fenwei:inst4.clock
clk50M => fenwei:inst5.clock
reset => controller:inst.reset
hold => controller:inst.hold
GREENA <= controller:inst.greenA
YELLOWA <= controller:inst.yellowA
REDB <= controller:inst.redB
GREENB <= controller:inst.greenB
YELLOWB <= controller:inst.yellowB
A0[0] <= display:inst6.display[0]
A0[1] <= display:inst6.display[1]
A0[2] <= display:inst6.display[2]
A0[3] <= display:inst6.display[3]
A0[4] <= display:inst6.display[4]
A0[5] <= display:inst6.display[5]
A0[6] <= display:inst6.display[6]
A1[0] <= display:inst1.display[0]
A1[1] <= display:inst1.display[1]
A1[2] <= display:inst1.display[2]
A1[3] <= display:inst1.display[3]
A1[4] <= display:inst1.display[4]
A1[5] <= display:inst1.display[5]
A1[6] <= display:inst1.display[6]
B0[0] <= display:inst8.display[0]
B0[1] <= display:inst8.display[1]
B0[2] <= display:inst8.display[2]
B0[3] <= display:inst8.display[3]
B0[4] <= display:inst8.display[4]
B0[5] <= display:inst8.display[5]
B0[6] <= display:inst8.display[6]
B1[0] <= display:inst7.display[0]
B1[1] <= display:inst7.display[1]
B1[2] <= display:inst7.display[2]
B1[3] <= display:inst7.display[3]
B1[4] <= display:inst7.display[4]
B1[5] <= display:inst7.display[5]
B1[6] <= display:inst7.display[6]


|traffic_controller|controller:inst
clock => numB[0]~reg0.CLK
clock => numB[1]~reg0.CLK
clock => numB[2]~reg0.CLK
clock => numB[3]~reg0.CLK
clock => numB[4]~reg0.CLK
clock => numA[0]~reg0.CLK
clock => numA[1]~reg0.CLK
clock => numA[2]~reg0.CLK
clock => numA[3]~reg0.CLK
clock => numA[4]~reg0.CLK
clock => yellowB~reg0.CLK
clock => yellowA~reg0.CLK
clock => greenB~reg0.CLK
clock => greenA~reg0.CLK
clock => redB~reg0.CLK
clock => redA~reg0.CLK
clock => flash~reg0.CLK
clock => countnum[0].CLK
clock => countnum[1].CLK
clock => countnum[2].CLK
clock => countnum[3].CLK
clock => countnum[4].CLK
clock => countnum[5].CLK
reset => countnum[0].ACLR
reset => countnum[1].ACLR
reset => countnum[2].ACLR
reset => countnum[3].ACLR
reset => countnum[4].ACLR
reset => countnum[5].ACLR
reset => flash~reg0.ENA
hold => redA~1.OUTPUTSELECT
hold => redB~0.OUTPUTSELECT
hold => greenA~0.OUTPUTSELECT
hold => greenB~1.OUTPUTSELECT
hold => yellowA~1.OUTPUTSELECT
hold => yellowB~1.OUTPUTSELECT
hold => numB[1]~reg0.ENA
hold => numB[0]~reg0.ENA
hold => numB[2]~reg0.ENA
hold => numB[3]~reg0.ENA
hold => numB[4]~reg0.ENA
hold => numA[0]~reg0.ENA
hold => numA[1]~reg0.ENA
hold => numA[2]~reg0.ENA
hold => numA[3]~reg0.ENA
hold => numA[4]~reg0.ENA
hold => flash~reg0.DATAIN
hold => countnum[0].ENA
hold => countnum[1].ENA
hold => countnum[2].ENA
hold => countnum[3].ENA
hold => countnum[4].ENA
hold => countnum[5].ENA
flash <= flash~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[0] <= numA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[1] <= numA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[2] <= numA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[3] <= numA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[4] <= numA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[0] <= numB[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[1] <= numB[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[2] <= numB[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[3] <= numB[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[4] <= numB[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
redA <= redA~reg0.DB_MAX_OUTPUT_PORT_TYPE
greenA <= greenA~reg0.DB_MAX_OUTPUT_PORT_TYPE
yellowA <= yellowA~reg0.DB_MAX_OUTPUT_PORT_TYPE
redB <= redB~reg0.DB_MAX_OUTPUT_PORT_TYPE
greenB <= greenB~reg0.DB_MAX_OUTPUT_PORT_TYPE
yellowB <= yellowB~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|frequency1Hz:inst2
clk20Hz => clk.CLK
clk20Hz => tout[0].CLK
clk20Hz => tout[1].CLK
clk20Hz => tout[2].CLK
clk20Hz => tout[3].CLK
clk1Hz <= clk.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|frequency20Hz:inst3
clk50M => clk.CLK
clk50M => tout[0].CLK
clk50M => tout[1].CLK
clk50M => tout[2].CLK
clk50M => tout[3].CLK
clk50M => tout[4].CLK
clk50M => tout[5].CLK
clk50M => tout[6].CLK
clk50M => tout[7].CLK
clk50M => tout[8].CLK
clk50M => tout[9].CLK
clk50M => tout[10].CLK
clk50M => tout[11].CLK
clk50M => tout[12].CLK
clk50M => tout[13].CLK
clk50M => tout[14].CLK
clk50M => tout[15].CLK
clk50M => tout[16].CLK
clk50M => tout[17].CLK
clk50M => tout[18].CLK
clk50M => tout[19].CLK
clk50M => tout[20].CLK
clk20Hz <= clk.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|display:inst6
clock => display[0]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[5]~reg0.CLK
clock => display[6]~reg0.CLK
clock => timeout[0].CLK
clock => timeout[1].CLK
clock => timeout[2].CLK
clock => timeout[3].CLK
clock => timeout[4].CLK
flash => timeout~5.OUTPUTSELECT
flash => timeout~6.OUTPUTSELECT
flash => timeout~7.OUTPUTSELECT
flash => timeout~8.OUTPUTSELECT
flash => timeout~9.OUTPUTSELECT
qin[0] => Mux0.IN19
qin[0] => Mux1.IN19
qin[0] => Mux2.IN19
qin[0] => Mux3.IN19
qin[0] => Mux4.IN19
qin[0] => Mux5.IN19
qin[0] => Mux6.IN19
qin[1] => Mux0.IN18
qin[1] => Mux1.IN18
qin[1] => Mux2.IN18
qin[1] => Mux3.IN18
qin[1] => Mux4.IN18
qin[1] => Mux5.IN18
qin[1] => Mux6.IN18
qin[2] => Mux0.IN17
qin[2] => Mux1.IN17
qin[2] => Mux2.IN17
qin[2] => Mux3.IN17
qin[2] => Mux4.IN17
qin[2] => Mux5.IN17
qin[2] => Mux6.IN17
qin[3] => Mux0.IN16
qin[3] => Mux1.IN16
qin[3] => Mux2.IN16
qin[3] => Mux3.IN16
qin[3] => Mux4.IN16
qin[3] => Mux5.IN16
qin[3] => Mux6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|fenwei:inst4
clock => numB[0]~reg0.CLK
clock => numB[1]~reg0.CLK
clock => numB[2]~reg0.CLK
clock => numB[3]~reg0.CLK
clock => numA[0]~reg0.CLK
clock => numA[1]~reg0.CLK
clock => numA[2]~reg0.CLK
clock => numA[3]~reg0.CLK
numin[0] => LessThan0.IN10
numin[0] => LessThan1.IN10
numin[0] => LessThan2.IN10
numin[0] => numB[0]~reg0.DATAIN
numin[1] => LessThan0.IN9
numin[1] => Add0.IN8
numin[1] => LessThan1.IN9
numin[1] => LessThan2.IN9
numin[1] => Add2.IN8
numin[1] => numB~2.DATAA
numin[1] => numB~5.DATAB
numin[2] => LessThan0.IN8
numin[2] => Add0.IN7
numin[2] => LessThan1.IN8
numin[2] => Add1.IN6
numin[2] => LessThan2.IN8
numin[2] => Add2.IN7
numin[2] => numB~1.DATAA
numin[3] => LessThan0.IN7
numin[3] => Add0.IN6
numin[3] => LessThan1.IN7
numin[3] => Add1.IN5
numin[3] => LessThan2.IN7
numin[3] => Add2.IN6
numin[3] => numB~0.DATAA
numin[4] => LessThan0.IN6
numin[4] => Add0.IN5
numin[4] => LessThan1.IN6
numin[4] => Add1.IN4
numin[4] => LessThan2.IN6
numin[4] => Add2.IN5
numA[0] <= numA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[1] <= numA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[2] <= numA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[3] <= numA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[0] <= numB[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[1] <= numB[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[2] <= numB[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[3] <= numB[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|display:inst1
clock => display[0]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[5]~reg0.CLK
clock => display[6]~reg0.CLK
clock => timeout[0].CLK
clock => timeout[1].CLK
clock => timeout[2].CLK
clock => timeout[3].CLK
clock => timeout[4].CLK
flash => timeout~5.OUTPUTSELECT
flash => timeout~6.OUTPUTSELECT
flash => timeout~7.OUTPUTSELECT
flash => timeout~8.OUTPUTSELECT
flash => timeout~9.OUTPUTSELECT
qin[0] => Mux0.IN19
qin[0] => Mux1.IN19
qin[0] => Mux2.IN19
qin[0] => Mux3.IN19
qin[0] => Mux4.IN19
qin[0] => Mux5.IN19
qin[0] => Mux6.IN19
qin[1] => Mux0.IN18
qin[1] => Mux1.IN18
qin[1] => Mux2.IN18
qin[1] => Mux3.IN18
qin[1] => Mux4.IN18
qin[1] => Mux5.IN18
qin[1] => Mux6.IN18
qin[2] => Mux0.IN17
qin[2] => Mux1.IN17
qin[2] => Mux2.IN17
qin[2] => Mux3.IN17
qin[2] => Mux4.IN17
qin[2] => Mux5.IN17
qin[2] => Mux6.IN17
qin[3] => Mux0.IN16
qin[3] => Mux1.IN16
qin[3] => Mux2.IN16
qin[3] => Mux3.IN16
qin[3] => Mux4.IN16
qin[3] => Mux5.IN16
qin[3] => Mux6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|display:inst8
clock => display[0]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[5]~reg0.CLK
clock => display[6]~reg0.CLK
clock => timeout[0].CLK
clock => timeout[1].CLK
clock => timeout[2].CLK
clock => timeout[3].CLK
clock => timeout[4].CLK
flash => timeout~5.OUTPUTSELECT
flash => timeout~6.OUTPUTSELECT
flash => timeout~7.OUTPUTSELECT
flash => timeout~8.OUTPUTSELECT
flash => timeout~9.OUTPUTSELECT
qin[0] => Mux0.IN19
qin[0] => Mux1.IN19
qin[0] => Mux2.IN19
qin[0] => Mux3.IN19
qin[0] => Mux4.IN19
qin[0] => Mux5.IN19
qin[0] => Mux6.IN19
qin[1] => Mux0.IN18
qin[1] => Mux1.IN18
qin[1] => Mux2.IN18
qin[1] => Mux3.IN18
qin[1] => Mux4.IN18
qin[1] => Mux5.IN18
qin[1] => Mux6.IN18
qin[2] => Mux0.IN17
qin[2] => Mux1.IN17
qin[2] => Mux2.IN17
qin[2] => Mux3.IN17
qin[2] => Mux4.IN17
qin[2] => Mux5.IN17
qin[2] => Mux6.IN17
qin[3] => Mux0.IN16
qin[3] => Mux1.IN16
qin[3] => Mux2.IN16
qin[3] => Mux3.IN16
qin[3] => Mux4.IN16
qin[3] => Mux5.IN16
qin[3] => Mux6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|fenwei:inst5
clock => numB[0]~reg0.CLK
clock => numB[1]~reg0.CLK
clock => numB[2]~reg0.CLK
clock => numB[3]~reg0.CLK
clock => numA[0]~reg0.CLK
clock => numA[1]~reg0.CLK
clock => numA[2]~reg0.CLK
clock => numA[3]~reg0.CLK
numin[0] => LessThan0.IN10
numin[0] => LessThan1.IN10
numin[0] => LessThan2.IN10
numin[0] => numB[0]~reg0.DATAIN
numin[1] => LessThan0.IN9
numin[1] => Add0.IN8
numin[1] => LessThan1.IN9
numin[1] => LessThan2.IN9
numin[1] => Add2.IN8
numin[1] => numB~2.DATAA
numin[1] => numB~5.DATAB
numin[2] => LessThan0.IN8
numin[2] => Add0.IN7
numin[2] => LessThan1.IN8
numin[2] => Add1.IN6
numin[2] => LessThan2.IN8
numin[2] => Add2.IN7
numin[2] => numB~1.DATAA
numin[3] => LessThan0.IN7
numin[3] => Add0.IN6
numin[3] => LessThan1.IN7
numin[3] => Add1.IN5
numin[3] => LessThan2.IN7
numin[3] => Add2.IN6
numin[3] => numB~0.DATAA
numin[4] => LessThan0.IN6
numin[4] => Add0.IN5
numin[4] => LessThan1.IN6
numin[4] => Add1.IN4
numin[4] => LessThan2.IN6
numin[4] => Add2.IN5
numA[0] <= numA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[1] <= numA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[2] <= numA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[3] <= numA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[0] <= numB[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[1] <= numB[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[2] <= numB[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[3] <= numB[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_controller|display:inst7
clock => display[0]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[5]~reg0.CLK
clock => display[6]~reg0.CLK
clock => timeout[0].CLK
clock => timeout[1].CLK
clock => timeout[2].CLK
clock => timeout[3].CLK
clock => timeout[4].CLK
flash => timeout~5.OUTPUTSELECT
flash => timeout~6.OUTPUTSELECT
flash => timeout~7.OUTPUTSELECT
flash => timeout~8.OUTPUTSELECT
flash => timeout~9.OUTPUTSELECT
qin[0] => Mux0.IN19
qin[0] => Mux1.IN19
qin[0] => Mux2.IN19
qin[0] => Mux3.IN19
qin[0] => Mux4.IN19
qin[0] => Mux5.IN19
qin[0] => Mux6.IN19
qin[1] => Mux0.IN18
qin[1] => Mux1.IN18
qin[1] => Mux2.IN18
qin[1] => Mux3.IN18
qin[1] => Mux4.IN18
qin[1] => Mux5.IN18
qin[1] => Mux6.IN18
qin[2] => Mux0.IN17
qin[2] => Mux1.IN17
qin[2] => Mux2.IN17
qin[2] => Mux3.IN17
qin[2] => Mux4.IN17
qin[2] => Mux5.IN17
qin[2] => Mux6.IN17
qin[3] => Mux0.IN16
qin[3] => Mux1.IN16
qin[3] => Mux2.IN16
qin[3] => Mux3.IN16
qin[3] => Mux4.IN16
qin[3] => Mux5.IN16
qin[3] => Mux6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE