fenwei.hier_info

实现交通灯控制器的vhdl编程

|fenwei
clock => numB[0]~reg0.CLK
clock => numB[1]~reg0.CLK
clock => numB[2]~reg0.CLK
clock => numB[3]~reg0.CLK
clock => numA[0]~reg0.CLK
clock => numA[1]~reg0.CLK
clock => numA[2]~reg0.CLK
clock => numA[3]~reg0.CLK
numin[0] => LessThan0.IN10
numin[0] => LessThan1.IN10
numin[0] => LessThan2.IN10
numin[0] => numB[0]~reg0.DATAIN
numin[1] => LessThan0.IN9
numin[1] => Add0.IN8
numin[1] => LessThan1.IN9
numin[1] => LessThan2.IN9
numin[1] => Add2.IN8
numin[1] => numB~2.DATAA
numin[1] => numB~5.DATAB
numin[2] => LessThan0.IN8
numin[2] => Add0.IN7
numin[2] => LessThan1.IN8
numin[2] => Add1.IN6
numin[2] => LessThan2.IN8
numin[2] => Add2.IN7
numin[2] => numB~1.DATAA
numin[3] => LessThan0.IN7
numin[3] => Add0.IN6
numin[3] => LessThan1.IN7
numin[3] => Add1.IN5
numin[3] => LessThan2.IN7
numin[3] => Add2.IN6
numin[3] => numB~0.DATAA
numin[4] => LessThan0.IN6
numin[4] => Add0.IN5
numin[4] => LessThan1.IN6
numin[4] => Add1.IN4
numin[4] => LessThan2.IN6
numin[4] => Add2.IN5
numA[0] <= numA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[1] <= numA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[2] <= numA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numA[3] <= numA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[0] <= numB[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[1] <= numB[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[2] <= numB[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numB[3] <= numB[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE