fenwei.tan.qmsg

实现交通灯控制器的vhdl编程

{ "Info" "ITDB_TSU_RESULT" "numA\[0\]~reg0 numin\[1\] clock 3.493 ns register " "Info: tsu for register \"numA\[0\]~reg0\" (data pin = \"numin\[1\]\", clock pin = \"clock\") is 3.493 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.220 ns + Longest pin register " "Info: + Longest pin to register delay is 6.220 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns numin\[1\] 1 PIN PIN_C23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_C23; Fanout = 4; PIN Node = 'numin\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { numin[1] } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.848 ns) + CELL(0.438 ns) 6.136 ns numA~135 2 COMB LCCOMB_X64_Y35_N16 1 " "Info: 2: + IC(4.848 ns) + CELL(0.438 ns) = 6.136 ns; Loc. = LCCOMB_X64_Y35_N16; Fanout = 1; COMB Node = 'numA~135'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.286 ns" { numin[1] numA~135 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.220 ns numA\[0\]~reg0 3 REG LCFF_X64_Y35_N17 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.220 ns; Loc. = LCFF_X64_Y35_N17; Fanout = 1; REG Node = 'numA\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { numA~135 numA[0]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.372 ns ( 22.06 % ) " "Info: Total cell delay = 1.372 ns ( 22.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.848 ns ( 77.94 % ) " "Info: Total interconnect delay = 4.848 ns ( 77.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.220 ns" { numin[1] numA~135 numA[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.220 ns" { numin[1] numin[1]~combout numA~135 numA[0]~reg0 } { 0.000ns 0.000ns 4.848ns 0.000ns } { 0.000ns 0.850ns 0.438ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.691 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns numA\[0\]~reg0 3 REG LCFF_X64_Y35_N17 1 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X64_Y35_N17; Fanout = 1; REG Node = 'numA\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl numA[0]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl numA[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl numA[0]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.220 ns" { numin[1] numA~135 numA[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.220 ns" { numin[1] numin[1]~combout numA~135 numA[0]~reg0 } { 0.000ns 0.000ns 4.848ns 0.000ns } { 0.000ns 0.850ns 0.438ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl numA[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl numA[0]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock numA\[1\] numA\[1\]~reg0 6.600 ns register " "Info: tco from clock \"clock\" to destination pin \"numA\[1\]\" through register \"numA\[1\]~reg0\" is 6.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.691 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns numA\[1\]~reg0 3 REG LCFF_X64_Y35_N21 1 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl numA[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.659 ns + Longest register pin " "Info: + Longest register to pin delay is 3.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numA\[1\]~reg0 1 REG LCFF_X64_Y35_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { numA[1]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.841 ns) + CELL(2.818 ns) 3.659 ns numA\[1\] 2 PIN PIN_B23 0 " "Info: 2: + IC(0.841 ns) + CELL(2.818 ns) = 3.659 ns; Loc. = PIN_B23; Fanout = 0; PIN Node = 'numA\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.659 ns" { numA[1]~reg0 numA[1] } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.818 ns ( 77.02 % ) " "Info: Total cell delay = 2.818 ns ( 77.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.841 ns ( 22.98 % ) " "Info: Total interconnect delay = 0.841 ns ( 22.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.659 ns" { numA[1]~reg0 numA[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.659 ns" { numA[1]~reg0 numA[1] } { 0.000ns 0.841ns } { 0.000ns 2.818ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl numA[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.659 ns" { numA[1]~reg0 numA[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.659 ns" { numA[1]~reg0 numA[1] } { 0.000ns 0.841ns } { 0.000ns 2.818ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "numA\[1\]~reg0 numin\[2\] clock -0.032 ns register " "Info: th for register \"numA\[1\]~reg0\" (data pin = \"numin\[2\]\", clock pin = \"clock\") is -0.032 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.691 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns numA\[1\]~reg0 3 REG LCFF_X64_Y35_N21 1 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl numA[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.989 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns numin\[2\] 1 PIN PIN_D13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 5; PIN Node = 'numin\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { numin[2] } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.150 ns) 2.905 ns LessThan1~68 2 COMB LCCOMB_X64_Y35_N20 1 " "Info: 2: + IC(1.776 ns) + CELL(0.150 ns) = 2.905 ns; Loc. = LCCOMB_X64_Y35_N20; Fanout = 1; COMB Node = 'LessThan1~68'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.926 ns" { numin[2] LessThan1~68 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.989 ns numA\[1\]~reg0 3 REG LCFF_X64_Y35_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.989 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { LessThan1~68 numA[1]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 40.58 % ) " "Info: Total cell delay = 1.213 ns ( 40.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.776 ns ( 59.42 % ) " "Info: Total interconnect delay = 1.776 ns ( 59.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.989 ns" { numin[2] LessThan1~68 numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.989 ns" { numin[2] numin[2]~combout LessThan1~68 numA[1]~reg0 } { 0.000ns 0.000ns 1.776ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl numA[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.989 ns" { numin[2] LessThan1~68 numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.989 ns" { numin[2] numin[2]~combout LessThan1~68 numA[1]~reg0 } { 0.000ns 0.000ns 1.776ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 04 16:16:12 2008 " "Info: Processing ended: Sat Oct 04 16:16:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}