fenwei.tan.rpt

实现交通灯控制器的vhdl编程

; N/A   ; None         ; 0.267 ns   ; numin[2] ; numB[3]~reg0 ; clock    ;
; N/A   ; None         ; 0.263 ns   ; numin[2] ; numA[0]~reg0 ; clock    ;
; N/A   ; None         ; 0.262 ns   ; numin[2] ; numA[1]~reg0 ; clock    ;
+-------+--------------+------------+----------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.600 ns   ; numA[1]~reg0 ; numA[1] ; clock      ;
; N/A   ; None         ; 6.518 ns   ; numB[1]~reg0 ; numB[1] ; clock      ;
; N/A   ; None         ; 6.468 ns   ; numB[2]~reg0 ; numB[2] ; clock      ;
; N/A   ; None         ; 6.375 ns   ; numB[3]~reg0 ; numB[3] ; clock      ;
; N/A   ; None         ; 6.360 ns   ; numA[0]~reg0 ; numA[0] ; clock      ;
; N/A   ; None         ; 6.081 ns   ; numB[0]~reg0 ; numB[0] ; clock      ;
+-------+--------------+------------+--------------+---------+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+----------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To           ; To Clock ;
+---------------+-------------+-----------+----------+--------------+----------+
; N/A           ; None        ; -0.032 ns ; numin[2] ; numA[1]~reg0 ; clock    ;
; N/A           ; None        ; -0.033 ns ; numin[2] ; numA[0]~reg0 ; clock    ;
; N/A           ; None        ; -0.037 ns ; numin[2] ; numB[1]~reg0 ; clock    ;
; N/A           ; None        ; -0.037 ns ; numin[2] ; numB[3]~reg0 ; clock    ;
; N/A           ; None        ; -0.038 ns ; numin[2] ; numB[2]~reg0 ; clock    ;
; N/A           ; None        ; -0.261 ns ; numin[4] ; numA[1]~reg0 ; clock    ;
; N/A           ; None        ; -0.264 ns ; numin[4] ; numA[0]~reg0 ; clock    ;
; N/A           ; None        ; -0.270 ns ; numin[4] ; numB[1]~reg0 ; clock    ;
; N/A           ; None        ; -0.270 ns ; numin[4] ; numB[3]~reg0 ; clock    ;
; N/A           ; None        ; -0.271 ns ; numin[4] ; numB[2]~reg0 ; clock    ;
; N/A           ; None        ; -2.535 ns ; numin[0] ; numB[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.135 ns ; numin[3] ; numA[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.135 ns ; numin[3] ; numA[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.138 ns ; numin[3] ; numB[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.141 ns ; numin[3] ; numB[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.142 ns ; numin[3] ; numB[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.256 ns ; numin[1] ; numB[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.259 ns ; numin[1] ; numB[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.259 ns ; numin[1] ; numB[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.263 ns ; numin[1] ; numA[0]~reg0 ; clock    ;
+---------------+-------------+-----------+----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Oct 04 16:16:11 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenwei -c fenwei --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clock"
Info: tsu for register "numA[0]~reg0" (data pin = "numin[1]", clock pin = "clock") is 3.493 ns
    Info: + Longest pin to register delay is 6.220 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_C23; Fanout = 4; PIN Node = 'numin[1]'
        Info: 2: + IC(4.848 ns) + CELL(0.438 ns) = 6.136 ns; Loc. = LCCOMB_X64_Y35_N16; Fanout = 1; COMB Node = 'numA~135'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.220 ns; Loc. = LCFF_X64_Y35_N17; Fanout = 1; REG Node = 'numA[0]~reg0'
        Info: Total cell delay = 1.372 ns ( 22.06 % )
        Info: Total interconnect delay = 4.848 ns ( 77.94 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.691 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X64_Y35_N17; Fanout = 1; REG Node = 'numA[0]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.08 % )
        Info: Total interconnect delay = 1.155 ns ( 42.92 % )
Info: tco from clock "clock" to destination pin "numA[1]" through register "numA[1]~reg0" is 6.600 ns
    Info: + Longest clock path from clock "clock" to source register is 2.691 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA[1]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.08 % )
        Info: Total interconnect delay = 1.155 ns ( 42.92 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.659 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA[1]~reg0'
        Info: 2: + IC(0.841 ns) + CELL(2.818 ns) = 3.659 ns; Loc. = PIN_B23; Fanout = 0; PIN Node = 'numA[1]'
        Info: Total cell delay = 2.818 ns ( 77.02 % )
        Info: Total interconnect delay = 0.841 ns ( 22.98 % )
Info: th for register "numA[1]~reg0" (data pin = "numin[2]", clock pin = "clock") is -0.032 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.691 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA[1]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.08 % )
        Info: Total interconnect delay = 1.155 ns ( 42.92 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.989 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 5; PIN Node = 'numin[2]'
        Info: 2: + IC(1.776 ns) + CELL(0.150 ns) = 2.905 ns; Loc. = LCCOMB_X64_Y35_N20; Fanout = 1; COMB Node = 'LessThan1~68'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.989 ns; Loc. = LCFF_X64_Y35_N21; Fanout = 1; REG Node = 'numA[1]~reg0'
        Info: Total cell delay = 1.213 ns ( 40.58 % )
        Info: Total interconnect delay = 1.776 ns ( 59.42 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Oct 04 16:16:12 2008
    Info: Elapsed time: 00:00:01