fenwei.vhd

来自「实现交通灯控制器的vhdl编程」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenwei is
port( clock : in std_logic;   --时钟采用50MHz
      numin : in integer range 0 to 30;
      numA,numB : out integer range 0 to 15);
end entity;
architecture behav of fenwei is
begin
process(clock)
begin
  if rising_edge(clock) then
    if numin>=30 then
      numA<=3;   --提取显示的十位数
      numB<=numin-30;   --提取显示的个位数
    elsif numin>=20 then
      numA<=2;
      numB<=numin-20;
    elsif numin>=10 then
      numA<=1;
      numB<=numin-10;
    else
      numA<=0;
      numB<=numin;
    end if;
  end if;
end process;
end behav;