traffic_controller.map.rpt

实现交通灯控制器的vhdl编程

; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |traffic_controller|display:inst7|timeout[4] ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic_controller|controller:inst|greenB   ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |traffic_controller|controller:inst|numA[3]  ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |traffic_controller|controller:inst|numB[0]  ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |traffic_controller|fenwei:inst4|numB[2]     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |traffic_controller|fenwei:inst5|numB[2]     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+


+---------------------------------------------+
; Source assignments for controller:inst      ;
+----------------+-------+------+-------------+
; Assignment     ; Value ; From ; To          ;
+----------------+-------+------+-------------+
; POWER_UP_LEVEL ; Low   ; -    ; countnum[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[4] ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[5] ;
+----------------+-------+------+-------------+


+-------------------------------------------+
; Source assignments for frequency1Hz:inst2 ;
+----------------+-------+------+-----------+
; Assignment     ; Value ; From ; To        ;
+----------------+-------+------+-----------+
; POWER_UP_LEVEL ; Low   ; -    ; tout[0]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[1]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[2]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[3]   ;
+----------------+-------+------+-----------+


+--------------------------------------------+
; Source assignments for frequency20Hz:inst3 ;
+----------------+-------+------+------------+
; Assignment     ; Value ; From ; To         ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; Low   ; -    ; tout[0]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[1]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[2]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[3]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[4]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[5]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[6]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[7]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[8]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[9]    ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[10]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[11]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[12]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[13]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[14]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[15]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[16]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[17]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[18]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[19]   ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[20]   ;
+----------------+-------+------+------------+


+--------------------------------------------+
; Source assignments for display:inst6       ;
+----------------+-------+------+------------+
; Assignment     ; Value ; From ; To         ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; Low   ; -    ; timeout[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[4] ;
+----------------+-------+------+------------+


+--------------------------------------------+
; Source assignments for display:inst1       ;
+----------------+-------+------+------------+
; Assignment     ; Value ; From ; To         ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; Low   ; -    ; timeout[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[4] ;
+----------------+-------+------+------------+


+--------------------------------------------+
; Source assignments for display:inst8       ;
+----------------+-------+------+------------+
; Assignment     ; Value ; From ; To         ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; Low   ; -    ; timeout[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[4] ;
+----------------+-------+------+------------+


+--------------------------------------------+
; Source assignments for display:inst7       ;
+----------------+-------+------+------------+
; Assignment     ; Value ; From ; To         ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; Low   ; -    ; timeout[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; timeout[4] ;
+----------------+-------+------+------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Oct 04 16:17:14 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic_controller -c traffic_controller
Info: Found 1 design units, including 1 entities, in source file traffic_controller.bdf
    Info: Found entity 1: traffic_controller
Info: Found 2 design units, including 1 entities, in source file frequency20Hz/frequency20Hz.vhd
    Info: Found design unit 1: frequency20Hz-behav
    Info: Found entity 1: frequency20Hz
Info: Found 2 design units, including 1 entities, in source file frequency1Hz/frequency1Hz.vhd
    Info: Found design unit 1: frequency1Hz-behav
    Info: Found entity 1: frequency1Hz
Info: Found 2 design units, including 1 entities, in source file fenwei/fenwei.vhd
    Info: Found design unit 1: fenwei-behav
    Info: Found entity 1: fenwei
Info: Found 2 design units, including 1 entities, in source file display/display.vhd
    Info: Found design unit 1: display-behav
    Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file controller/controller.vhd
    Info: Found design unit 1: controller-behav
    Info: Found entity 1: controller
Info: Elaborating entity "traffic_controller" for the top level hierarchy
Info: Elaborating entity "controller" for hierarchy "controller:inst"
Warning (10492): VHDL Process Statement warning at controller.vhd(19): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "frequency1Hz" for hierarchy "frequency1Hz:inst2"
Info: Elaborating entity "frequency20Hz" for hierarchy "frequency20Hz:inst3"
Info: Elaborating entity "display" for hierarchy "display:inst6"
Info: Elaborating entity "fenwei" for hierarchy "fenwei:inst4"
Warning: Reduced register "fenwei:inst5|numA[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fenwei:inst5|numA[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "fenwei:inst4|numA[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fenwei:inst4|numA[3]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "display:inst1|timeout[0]" merged to single register "display:inst7|timeout[0]"
    Info: Duplicate register "display:inst6|timeout[0]" merged to single register "display:inst7|timeout[0]"
    Info: Duplicate register "display:inst8|timeout[0]" merged to single register "display:inst7|timeout[0]"
    Info: Duplicate register "display:inst1|timeout[1]" merged to single register "display:inst7|timeout[1]"
    Info: Duplicate register "display:inst6|timeout[1]" merged to single register "display:inst7|timeout[1]"
    Info: Duplicate register "display:inst8|timeout[1]" merged to single register "display:inst7|timeout[1]"
    Info: Duplicate register "display:inst1|timeout[2]" merged to single register "display:inst7|timeout[2]"
    Info: Duplicate register "display:inst6|timeout[2]" merged to single register "display:inst7|timeout[2]"
    Info: Duplicate register "display:inst8|timeout[2]" merged to single register "display:inst7|timeout[2]"
    Info: Duplicate register "display:inst1|timeout[3]" merged to single register "display:inst7|timeout[3]"
    Info: Duplicate register "display:inst6|timeout[3]" merged to single register "display:inst7|timeout[3]"
    Info: Duplicate register "display:inst8|timeout[3]" merged to single register "display:inst7|timeout[3]"
    Info: Duplicate register "display:inst1|timeout[4]" merged to single register "display:inst7|timeout[4]"
    Info: Duplicate register "display:inst6|timeout[4]" merged to single register "display:inst7|timeout[4]"
    Info: Duplicate register "display:inst8|timeout[4]" merged to single register "display:inst7|timeout[4]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "display:inst7|display[3]" merged to single register "display:inst7|display[0]"
    Info: Duplicate register "display:inst1|display[1]" merged to single register "display:inst7|display[1]"
    Info: Duplicate register "display:inst1|display[3]" merged to single register "display:inst1|display[0]"
Info: Implemented 185 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 34 output pins
    Info: Implemented 148 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Sat Oct 04 16:17:17 2008
    Info: Elapsed time: 00:00:04