controller.tan.qmsg

实现交通灯控制器的vhdl编程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register countnum\[4\] register numA\[1\]~reg0 373.69 MHz 2.676 ns Internal " "Info: Clock \"clock\" has Internal fmax of 373.69 MHz between source register \"countnum\[4\]\" and destination register \"numA\[1\]~reg0\" (period= 2.676 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.464 ns + Longest register register " "Info: + Longest register to register delay is 2.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns countnum\[4\] 1 REG LCFF_X17_Y30_N21 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y30_N21; Fanout = 7; REG Node = 'countnum\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countnum[4] } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.271 ns) 0.599 ns LessThan0~154 2 COMB LCCOMB_X17_Y30_N22 2 " "Info: 2: + IC(0.328 ns) + CELL(0.271 ns) = 0.599 ns; Loc. = LCCOMB_X17_Y30_N22; Fanout = 2; COMB Node = 'LessThan0~154'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.599 ns" { countnum[4] LessThan0~154 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.420 ns) 1.277 ns LessThan0~156 3 COMB LCCOMB_X17_Y30_N24 6 " "Info: 3: + IC(0.258 ns) + CELL(0.420 ns) = 1.277 ns; Loc. = LCCOMB_X17_Y30_N24; Fanout = 6; COMB Node = 'LessThan0~156'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.678 ns" { LessThan0~154 LessThan0~156 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.684 ns) + CELL(0.419 ns) 2.380 ns numA~1760 4 COMB LCCOMB_X18_Y30_N26 1 " "Info: 4: + IC(0.684 ns) + CELL(0.419 ns) = 2.380 ns; Loc. = LCCOMB_X18_Y30_N26; Fanout = 1; COMB Node = 'numA~1760'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.103 ns" { LessThan0~156 numA~1760 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.464 ns numA\[1\]~reg0 5 REG LCFF_X18_Y30_N27 1 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.464 ns; Loc. = LCFF_X18_Y30_N27; Fanout = 1; REG Node = 'numA\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { numA~1760 numA[1]~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.194 ns ( 48.46 % ) " "Info: Total cell delay = 1.194 ns ( 48.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.270 ns ( 51.54 % ) " "Info: Total interconnect delay = 1.270 ns ( 51.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.464 ns" { countnum[4] LessThan0~154 LessThan0~156 numA~1760 numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.464 ns" { countnum[4] LessThan0~154 LessThan0~156 numA~1760 numA[1]~reg0 } { 0.000ns 0.328ns 0.258ns 0.684ns 0.000ns } { 0.000ns 0.271ns 0.420ns 0.419ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.667 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.013 ns) + CELL(0.537 ns) 2.667 ns numA\[1\]~reg0 3 REG LCFF_X18_Y30_N27 1 " "Info: 3: + IC(1.013 ns) + CELL(0.537 ns) = 2.667 ns; Loc. = LCFF_X18_Y30_N27; Fanout = 1; REG Node = 'numA\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.550 ns" { clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.59 % ) " "Info: Total cell delay = 1.536 ns ( 57.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.131 ns ( 42.41 % ) " "Info: Total interconnect delay = 1.131 ns ( 42.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.667 ns" { clock clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.667 ns" { clock clock~combout clock~clkctrl numA[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.013ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.665 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.537 ns) 2.665 ns countnum\[4\] 3 REG LCFF_X17_Y30_N21 7 " "Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X17_Y30_N21; Fanout = 7; REG Node = 'countnum\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.548 ns" { clock~clkctrl countnum[4] } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.64 % ) " "Info: Total cell delay = 1.536 ns ( 57.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.129 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.129 ns ( 42.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl countnum[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl countnum[4] } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.667 ns" { clock clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.667 ns" { clock clock~combout clock~clkctrl numA[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.013ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl countnum[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl countnum[4] } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.464 ns" { countnum[4] LessThan0~154 LessThan0~156 numA~1760 numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.464 ns" { countnum[4] LessThan0~154 LessThan0~156 numA~1760 numA[1]~reg0 } { 0.000ns 0.328ns 0.258ns 0.684ns 0.000ns } { 0.000ns 0.271ns 0.420ns 0.419ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.667 ns" { clock clock~clkctrl numA[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.667 ns" { clock clock~combout clock~clkctrl numA[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.013ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl countnum[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl countnum[4] } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "flash~reg0 reset clock 0.748 ns register " "Info: tsu for register \"flash~reg0\" (data pin = \"reset\", clock pin = \"clock\") is 0.748 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.449 ns + Longest pin register " "Info: + Longest pin to register delay is 3.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns reset 1 PIN PIN_P1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 2; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.947 ns) + CELL(0.419 ns) 3.365 ns flash~15 2 COMB LCCOMB_X16_Y30_N10 1 " "Info: 2: + IC(1.947 ns) + CELL(0.419 ns) = 3.365 ns; Loc. = LCCOMB_X16_Y30_N10; Fanout = 1; COMB Node = 'flash~15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.366 ns" { reset flash~15 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.449 ns flash~reg0 3 REG LCFF_X16_Y30_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.449 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { flash~15 flash~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.502 ns ( 43.55 % ) " "Info: Total cell delay = 1.502 ns ( 43.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.947 ns ( 56.45 % ) " "Info: Total interconnect delay = 1.947 ns ( 56.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.449 ns" { reset flash~15 flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.449 ns" { reset reset~combout flash~15 flash~reg0 } { 0.000ns 0.000ns 1.947ns 0.000ns } { 0.000ns 0.999ns 0.419ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.665 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.537 ns) 2.665 ns flash~reg0 3 REG LCFF_X16_Y30_N11 2 " "Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.548 ns" { clock~clkctrl flash~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.64 % ) " "Info: Total cell delay = 1.536 ns ( 57.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.129 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.129 ns ( 42.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl flash~reg0 } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.449 ns" { reset flash~15 flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.449 ns" { reset reset~combout flash~15 flash~reg0 } { 0.000ns 0.000ns 1.947ns 0.000ns } { 0.000ns 0.999ns 0.419ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl flash~reg0 } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock numB\[1\] numB\[1\]~reg0 7.195 ns register " "Info: tco from clock \"clock\" to destination pin \"numB\[1\]\" through register \"numB\[1\]~reg0\" is 7.195 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.665 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.537 ns) 2.665 ns numB\[1\]~reg0 3 REG LCFF_X16_Y30_N25 1 " "Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X16_Y30_N25; Fanout = 1; REG Node = 'numB\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.548 ns" { clock~clkctrl numB[1]~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.64 % ) " "Info: Total cell delay = 1.536 ns ( 57.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.129 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.129 ns ( 42.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl numB[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl numB[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.280 ns + Longest register pin " "Info: + Longest register to pin delay is 4.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numB\[1\]~reg0 1 REG LCFF_X16_Y30_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y30_N25; Fanout = 1; REG Node = 'numB\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { numB[1]~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.492 ns) + CELL(2.788 ns) 4.280 ns numB\[1\] 2 PIN PIN_D7 0 " "Info: 2: + IC(1.492 ns) + CELL(2.788 ns) = 4.280 ns; Loc. = PIN_D7; Fanout = 0; PIN Node = 'numB\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.280 ns" { numB[1]~reg0 numB[1] } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.788 ns ( 65.14 % ) " "Info: Total cell delay = 2.788 ns ( 65.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.492 ns ( 34.86 % ) " "Info: Total interconnect delay = 1.492 ns ( 34.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.280 ns" { numB[1]~reg0 numB[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.280 ns" { numB[1]~reg0 numB[1] } { 0.000ns 1.492ns } { 0.000ns 2.788ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl numB[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl numB[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.280 ns" { numB[1]~reg0 numB[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.280 ns" { numB[1]~reg0 numB[1] } { 0.000ns 1.492ns } { 0.000ns 2.788ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "flash~reg0 hold clock 0.258 ns register " "Info: th for register \"flash~reg0\" (data pin = \"hold\", clock pin = \"clock\") is 0.258 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.665 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.537 ns) 2.665 ns flash~reg0 3 REG LCFF_X16_Y30_N11 2 " "Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.548 ns" { clock~clkctrl flash~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.64 % ) " "Info: Total cell delay = 1.536 ns ( 57.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.129 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.129 ns ( 42.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl flash~reg0 } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.673 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns hold 1 PIN PIN_C13 23 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 23; PIN Node = 'hold'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hold } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.460 ns) + CELL(0.150 ns) 2.589 ns flash~15 2 COMB LCCOMB_X16_Y30_N10 1 " "Info: 2: + IC(1.460 ns) + CELL(0.150 ns) = 2.589 ns; Loc. = LCCOMB_X16_Y30_N10; Fanout = 1; COMB Node = 'flash~15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.610 ns" { hold flash~15 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.673 ns flash~reg0 3 REG LCFF_X16_Y30_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.673 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { flash~15 flash~reg0 } "NODE_NAME" } } { "controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 45.38 % ) " "Info: Total cell delay = 1.213 ns ( 45.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.460 ns ( 54.62 % ) " "Info: Total interconnect delay = 1.460 ns ( 54.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { hold flash~15 flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { hold hold~combout flash~15 flash~reg0 } { 0.000ns 0.000ns 1.460ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { clock clock~clkctrl flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { clock clock~combout clock~clkctrl flash~reg0 } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { hold flash~15 flash~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { hold hold~combout flash~15 flash~reg0 } { 0.000ns 0.000ns 1.460ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}