controller.tan.rpt

实现交通灯控制器的vhdl编程

; N/A   ; None         ; 7.093 ns   ; numA[1]~reg0 ; numA[1] ; clock      ;
; N/A   ; None         ; 7.029 ns   ; numB[2]~reg0 ; numB[2] ; clock      ;
; N/A   ; None         ; 6.980 ns   ; numA[0]~reg0 ; numA[0] ; clock      ;
; N/A   ; None         ; 6.939 ns   ; flash~reg0   ; flash   ; clock      ;
; N/A   ; None         ; 6.903 ns   ; redA~reg0    ; redA    ; clock      ;
; N/A   ; None         ; 6.883 ns   ; numB[0]~reg0 ; numB[0] ; clock      ;
; N/A   ; None         ; 6.808 ns   ; greenA~reg0  ; greenA  ; clock      ;
; N/A   ; None         ; 6.798 ns   ; redB~reg0    ; redB    ; clock      ;
; N/A   ; None         ; 6.708 ns   ; yellowA~reg0 ; yellowA ; clock      ;
; N/A   ; None         ; 6.672 ns   ; numB[3]~reg0 ; numB[3] ; clock      ;
; N/A   ; None         ; 6.672 ns   ; numA[4]~reg0 ; numA[4] ; clock      ;
; N/A   ; None         ; 6.639 ns   ; greenB~reg0  ; greenB  ; clock      ;
; N/A   ; None         ; 6.635 ns   ; numA[2]~reg0 ; numA[2] ; clock      ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; 0.258 ns  ; hold  ; flash~reg0   ; clock    ;
; N/A           ; None        ; 0.034 ns  ; hold  ; yellowB~reg0 ; clock    ;
; N/A           ; None        ; 0.033 ns  ; hold  ; greenB~reg0  ; clock    ;
; N/A           ; None        ; -0.010 ns ; hold  ; greenA~reg0  ; clock    ;
; N/A           ; None        ; -0.011 ns ; hold  ; yellowA~reg0 ; clock    ;
; N/A           ; None        ; -0.046 ns ; hold  ; redB~reg0    ; clock    ;
; N/A           ; None        ; -0.104 ns ; hold  ; redA~reg0    ; clock    ;
; N/A           ; None        ; -0.119 ns ; hold  ; countnum[0]  ; clock    ;
; N/A           ; None        ; -0.119 ns ; hold  ; countnum[4]  ; clock    ;
; N/A           ; None        ; -0.119 ns ; hold  ; countnum[3]  ; clock    ;
; N/A           ; None        ; -0.119 ns ; hold  ; countnum[1]  ; clock    ;
; N/A           ; None        ; -0.119 ns ; hold  ; numA[3]~reg0 ; clock    ;
; N/A           ; None        ; -0.119 ns ; hold  ; numA[4]~reg0 ; clock    ;
; N/A           ; None        ; -0.122 ns ; hold  ; numA[0]~reg0 ; clock    ;
; N/A           ; None        ; -0.122 ns ; hold  ; countnum[5]  ; clock    ;
; N/A           ; None        ; -0.122 ns ; hold  ; numB[1]~reg0 ; clock    ;
; N/A           ; None        ; -0.122 ns ; hold  ; numB[2]~reg0 ; clock    ;
; N/A           ; None        ; -0.153 ns ; hold  ; countnum[2]  ; clock    ;
; N/A           ; None        ; -0.153 ns ; hold  ; numA[1]~reg0 ; clock    ;
; N/A           ; None        ; -0.153 ns ; hold  ; numA[2]~reg0 ; clock    ;
; N/A           ; None        ; -0.153 ns ; hold  ; numB[0]~reg0 ; clock    ;
; N/A           ; None        ; -0.153 ns ; hold  ; numB[3]~reg0 ; clock    ;
; N/A           ; None        ; -0.153 ns ; hold  ; numB[4]~reg0 ; clock    ;
; N/A           ; None        ; -0.518 ns ; reset ; flash~reg0   ; clock    ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Oct 04 16:07:28 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off controller -c controller --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 373.69 MHz between source register "countnum[4]" and destination register "numA[1]~reg0" (period= 2.676 ns)
    Info: + Longest register to register delay is 2.464 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y30_N21; Fanout = 7; REG Node = 'countnum[4]'
        Info: 2: + IC(0.328 ns) + CELL(0.271 ns) = 0.599 ns; Loc. = LCCOMB_X17_Y30_N22; Fanout = 2; COMB Node = 'LessThan0~154'
        Info: 3: + IC(0.258 ns) + CELL(0.420 ns) = 1.277 ns; Loc. = LCCOMB_X17_Y30_N24; Fanout = 6; COMB Node = 'LessThan0~156'
        Info: 4: + IC(0.684 ns) + CELL(0.419 ns) = 2.380 ns; Loc. = LCCOMB_X18_Y30_N26; Fanout = 1; COMB Node = 'numA~1760'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.464 ns; Loc. = LCFF_X18_Y30_N27; Fanout = 1; REG Node = 'numA[1]~reg0'
        Info: Total cell delay = 1.194 ns ( 48.46 % )
        Info: Total interconnect delay = 1.270 ns ( 51.54 % )
    Info: - Smallest clock skew is 0.002 ns
        Info: + Shortest clock path from clock "clock" to destination register is 2.667 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'
            Info: 3: + IC(1.013 ns) + CELL(0.537 ns) = 2.667 ns; Loc. = LCFF_X18_Y30_N27; Fanout = 1; REG Node = 'numA[1]~reg0'
            Info: Total cell delay = 1.536 ns ( 57.59 % )
            Info: Total interconnect delay = 1.131 ns ( 42.41 % )
        Info: - Longest clock path from clock "clock" to source register is 2.665 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'
            Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X17_Y30_N21; Fanout = 7; REG Node = 'countnum[4]'
            Info: Total cell delay = 1.536 ns ( 57.64 % )
            Info: Total interconnect delay = 1.129 ns ( 42.36 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "flash~reg0" (data pin = "reset", clock pin = "clock") is 0.748 ns
    Info: + Longest pin to register delay is 3.449 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 2; PIN Node = 'reset'
        Info: 2: + IC(1.947 ns) + CELL(0.419 ns) = 3.365 ns; Loc. = LCCOMB_X16_Y30_N10; Fanout = 1; COMB Node = 'flash~15'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.449 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'
        Info: Total cell delay = 1.502 ns ( 43.55 % )
        Info: Total interconnect delay = 1.947 ns ( 56.45 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.665 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'
        Info: Total cell delay = 1.536 ns ( 57.64 % )
        Info: Total interconnect delay = 1.129 ns ( 42.36 % )
Info: tco from clock "clock" to destination pin "numB[1]" through register "numB[1]~reg0" is 7.195 ns
    Info: + Longest clock path from clock "clock" to source register is 2.665 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X16_Y30_N25; Fanout = 1; REG Node = 'numB[1]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.64 % )
        Info: Total interconnect delay = 1.129 ns ( 42.36 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.280 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y30_N25; Fanout = 1; REG Node = 'numB[1]~reg0'
        Info: 2: + IC(1.492 ns) + CELL(2.788 ns) = 4.280 ns; Loc. = PIN_D7; Fanout = 0; PIN Node = 'numB[1]'
        Info: Total cell delay = 2.788 ns ( 65.14 % )
        Info: Total interconnect delay = 1.492 ns ( 34.86 % )
Info: th for register "flash~reg0" (data pin = "hold", clock pin = "clock") is 0.258 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.665 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'
        Info: Total cell delay = 1.536 ns ( 57.64 % )
        Info: Total interconnect delay = 1.129 ns ( 42.36 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.673 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 23; PIN Node = 'hold'
        Info: 2: + IC(1.460 ns) + CELL(0.150 ns) = 2.589 ns; Loc. = LCCOMB_X16_Y30_N10; Fanout = 1; COMB Node = 'flash~15'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.673 ns; Loc. = LCFF_X16_Y30_N11; Fanout = 2; REG Node = 'flash~reg0'
        Info: Total cell delay = 1.213 ns ( 45.38 % )
        Info: Total interconnect delay = 1.460 ns ( 54.62 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Oct 04 16:07:29 2008
    Info: Elapsed time: 00:00:01