📄 controller.tan.rpt
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Timing Analyzer report for controller
Sat Oct 04 16:07:29 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clock'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 0.748 ns ; reset ; flash~reg0 ; -- ; clock ; 0 ;
; Worst-case tco ; N/A ; None ; 7.195 ns ; numB[1]~reg0 ; numB[1] ; clock ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.258 ns ; hold ; flash~reg0 ; -- ; clock ; 0 ;
; Clock Setup: 'clock' ; N/A ; None ; 373.69 MHz ( period = 2.676 ns ) ; countnum[4] ; numA[1]~reg0 ; clock ; clock ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock' ;
+-------+------------------------------------------------+-------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 373.69 MHz ( period = 2.676 ns ) ; countnum[4] ; numA[1]~reg0 ; clock ; clock ; None ; None ; 2.464 ns ;
; N/A ; 376.93 MHz ( period = 2.653 ns ) ; countnum[4] ; numA[2]~reg0 ; clock ; clock ; None ; None ; 2.441 ns ;
; N/A ; 379.36 MHz ( period = 2.636 ns ) ; countnum[4] ; numB[4]~reg0 ; clock ; clock ; None ; None ; 2.424 ns ;
; N/A ; 383.73 MHz ( period = 2.606 ns ) ; countnum[5] ; numB[4]~reg0 ; clock ; clock ; None ; None ; 2.394 ns ;
; N/A ; 384.47 MHz ( period = 2.601 ns ) ; countnum[5] ; numA[1]~reg0 ; clock ; clock ; None ; None ; 2.389 ns ;
; N/A ; 387.90 MHz ( period = 2.578 ns ) ; countnum[5] ; numA[2]~reg0 ; clock ; clock ; None ; None ; 2.366 ns ;
; N/A ; 387.90 MHz ( period = 2.578 ns ) ; countnum[4] ; yellowA~reg0 ; clock ; clock ; None ; None ; 2.369 ns ;
; N/A ; 389.41 MHz ( period = 2.568 ns ) ; countnum[3] ; numA[1]~reg0 ; clock ; clock ; None ; None ; 2.356 ns ;
; N/A ; 392.93 MHz ( period = 2.545 ns ) ; countnum[3] ; numA[2]~reg0 ; clock ; clock ; None ; None ; 2.333 ns ;
; N/A ; 395.57 MHz ( period = 2.528 ns ) ; countnum[3] ; numB[4]~reg0 ; clock ; clock ; None ; None ; 2.316 ns ;
; N/A ; 396.67 MHz ( period = 2.521 ns ) ; countnum[4] ; numA[3]~reg0 ; clock ; clock ; None ; None ; 2.307 ns ;
; N/A ; 396.67 MHz ( period = 2.521 ns ) ; countnum[4] ; numA[4]~reg0 ; clock ; clock ; None ; None ; 2.307 ns ;
; N/A ; 397.61 MHz ( period = 2.515 ns ) ; countnum[0] ; numB[1]~reg0 ; clock ; clock ; None ; None ; 2.301 ns ;
; N/A ; 397.61 MHz ( period = 2.515 ns ) ; countnum[0] ; numB[2]~reg0 ; clock ; clock ; None ; None ; 2.301 ns ;
; N/A ; 397.77 MHz ( period = 2.514 ns ) ; countnum[0] ; countnum[5] ; clock ; clock ; None ; None ; 2.300 ns ;
; N/A ; 399.52 MHz ( period = 2.503 ns ) ; countnum[5] ; yellowA~reg0 ; clock ; clock ; None ; None ; 2.294 ns ;
; N/A ; 402.74 MHz ( period = 2.483 ns ) ; countnum[5] ; numA[3]~reg0 ; clock ; clock ; None ; None ; 2.269 ns ;
; N/A ; 402.74 MHz ( period = 2.483 ns ) ; countnum[5] ; numA[4]~reg0 ; clock ; clock ; None ; None ; 2.269 ns ;
; N/A ; 404.86 MHz ( period = 2.470 ns ) ; countnum[3] ; yellowA~reg0 ; clock ; clock ; None ; None ; 2.261 ns ;
; N/A ; 413.39 MHz ( period = 2.419 ns ) ; countnum[1] ; numB[4]~reg0 ; clock ; clock ; None ; None ; 2.207 ns ;
; N/A ; 414.42 MHz ( period = 2.413 ns ) ; countnum[3] ; numA[3]~reg0 ; clock ; clock ; None ; None ; 2.199 ns ;
; N/A ; 414.42 MHz ( period = 2.413 ns ) ; countnum[3] ; numA[4]~reg0 ; clock ; clock ; None ; None ; 2.199 ns ;
; N/A ; 414.77 MHz ( period = 2.411 ns ) ; countnum[0] ; numB[4]~reg0 ; clock ; clock ; None ; None ; 2.199 ns ;
; N/A ; 415.97 MHz ( period = 2.404 ns ) ; countnum[2] ; countnum[5] ; clock ; clock ; None ; None ; 2.188 ns ;
; N/A ; 416.49 MHz ( period = 2.401 ns ) ; countnum[2] ; numB[4]~reg0 ; clock ; clock ; None ; None ; 2.187 ns ;
; N/A ; 416.84 MHz ( period = 2.399 ns ) ; countnum[2] ; numA[3]~reg0 ; clock ; clock ; None ; None ; 2.183 ns ;
; N/A ; 416.84 MHz ( period = 2.399 ns ) ; countnum[2] ; numA[4]~reg0 ; clock ; clock ; None ; None ; 2.183 ns ;
; N/A ; 417.54 MHz ( period = 2.395 ns ) ; countnum[4] ; countnum[5] ; clock ; clock ; None ; None ; 2.181 ns ;
; N/A ; 418.59 MHz ( period = 2.389 ns ) ; countnum[0] ; numB[3]~reg0 ; clock ; clock ; None ; None ; 2.177 ns ;
; N/A ; 419.64 MHz ( period = 2.383 ns ) ; countnum[0] ; yellowB~reg0 ; clock ; clock ; None ; None ; 2.171 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; countnum[0] ; numA[1]~reg0 ; clock ; clock ; None ; None ; 2.166 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; countnum[4] ; numB[3]~reg0 ; clock ; clock ; None ; None ; 2.164 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; countnum[0] ; greenB~reg0 ; clock ; clock ; None ; None ; 2.158 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; countnum[3] ; countnum[5] ; clock ; clock ; None ; None ; 2.145 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; countnum[1] ; countnum[5] ; clock ; clock ; None ; None ; 2.141 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; countnum[0] ; numA[2]~reg0 ; clock ; clock ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; countnum[5] ; numB[1]~reg0 ; clock ; clock ; None ; None ; 2.133 ns ;
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