📄 frequency20hz.tan.qmsg

📁 实现交通灯控制器的vhdl编程
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk50M " "Info: Assuming node \"clk50M\" is an undefined clock" {  } { { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 5 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk50M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk50M register tout\[0\] register tout\[20\] 276.09 MHz 3.622 ns Internal " "Info: Clock \"clk50M\" has Internal fmax of 276.09 MHz between source register \"tout\[0\]\" and destination register \"tout\[20\]\" (period= 3.622 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.413 ns + Longest register register " "Info: + Longest register to register delay is 3.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tout\[0\] 1 REG LCFF_X54_Y24_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y24_N13; Fanout = 3; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tout[0] } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.333 ns) + CELL(0.414 ns) 0.747 ns Add0~253 2 COMB LCCOMB_X54_Y24_N12 2 " "Info: 2: + IC(0.333 ns) + CELL(0.414 ns) = 0.747 ns; Loc. = LCCOMB_X54_Y24_N12; Fanout = 2; COMB Node = 'Add0~253'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.747 ns" { tout[0] Add0~253 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 0.906 ns Add0~255 3 COMB LCCOMB_X54_Y24_N14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.159 ns) = 0.906 ns; Loc. = LCCOMB_X54_Y24_N14; Fanout = 2; COMB Node = 'Add0~255'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~253 Add0~255 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.977 ns Add0~257 4 COMB LCCOMB_X54_Y24_N16 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.977 ns; Loc. = LCCOMB_X54_Y24_N16; Fanout = 2; COMB Node = 'Add0~257'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~255 Add0~257 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.048 ns Add0~259 5 COMB LCCOMB_X54_Y24_N18 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.048 ns; Loc. = LCCOMB_X54_Y24_N18; Fanout = 2; COMB Node = 'Add0~259'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~257 Add0~259 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.119 ns Add0~261 6 COMB LCCOMB_X54_Y24_N20 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.119 ns; Loc. = LCCOMB_X54_Y24_N20; Fanout = 2; COMB Node = 'Add0~261'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~259 Add0~261 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.190 ns Add0~263 7 COMB LCCOMB_X54_Y24_N22 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.190 ns; Loc. = LCCOMB_X54_Y24_N22; Fanout = 2; COMB Node = 'Add0~263'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~261 Add0~263 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.261 ns Add0~265 8 COMB LCCOMB_X54_Y24_N24 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.261 ns; Loc. = LCCOMB_X54_Y24_N24; Fanout = 2; COMB Node = 'Add0~265'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~263 Add0~265 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.332 ns Add0~267 9 COMB LCCOMB_X54_Y24_N26 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.332 ns; Loc. = LCCOMB_X54_Y24_N26; Fanout = 2; COMB Node = 'Add0~267'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~265 Add0~267 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.403 ns Add0~269 10 COMB LCCOMB_X54_Y24_N28 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.403 ns; Loc. = LCCOMB_X54_Y24_N28; Fanout = 2; COMB Node = 'Add0~269'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~267 Add0~269 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 1.549 ns Add0~271 11 COMB LCCOMB_X54_Y24_N30 2 " "Info: 11: + IC(0.000 ns) + CELL(0.146 ns) = 1.549 ns; Loc. = LCCOMB_X54_Y24_N30; Fanout = 2; COMB Node = 'Add0~271'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.146 ns" { Add0~269 Add0~271 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.620 ns Add0~273 12 COMB LCCOMB_X54_Y23_N0 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.620 ns; Loc. = LCCOMB_X54_Y23_N0; Fanout = 2; COMB Node = 'Add0~273'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~271 Add0~273 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.691 ns Add0~275 13 COMB LCCOMB_X54_Y23_N2 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.691 ns; Loc. = LCCOMB_X54_Y23_N2; Fanout = 2; COMB Node = 'Add0~275'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~273 Add0~275 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.762 ns Add0~277 14 COMB LCCOMB_X54_Y23_N4 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.762 ns; Loc. = LCCOMB_X54_Y23_N4; Fanout = 2; COMB Node = 'Add0~277'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~275 Add0~277 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.833 ns Add0~279 15 COMB LCCOMB_X54_Y23_N6 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.833 ns; Loc. = LCCOMB_X54_Y23_N6; Fanout = 2; COMB Node = 'Add0~279'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~277 Add0~279 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.904 ns Add0~281 16 COMB LCCOMB_X54_Y23_N8 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.904 ns; Loc. = LCCOMB_X54_Y23_N8; Fanout = 2; COMB Node = 'Add0~281'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~279 Add0~281 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.975 ns Add0~283 17 COMB LCCOMB_X54_Y23_N10 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 1.975 ns; Loc. = LCCOMB_X54_Y23_N10; Fanout = 2; COMB Node = 'Add0~283'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~281 Add0~283 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.046 ns Add0~285 18 COMB LCCOMB_X54_Y23_N12 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.046 ns; Loc. = LCCOMB_X54_Y23_N12; Fanout = 2; COMB Node = 'Add0~285'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~283 Add0~285 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.205 ns Add0~287 19 COMB LCCOMB_X54_Y23_N14 2 " "Info: 19: + IC(0.000 ns) + CELL(0.159 ns) = 2.205 ns; Loc. = LCCOMB_X54_Y23_N14; Fanout = 2; COMB Node = 'Add0~287'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~285 Add0~287 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.276 ns Add0~289 20 COMB LCCOMB_X54_Y23_N16 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.276 ns; Loc. = LCCOMB_X54_Y23_N16; Fanout = 2; COMB Node = 'Add0~289'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~287 Add0~289 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.347 ns Add0~291 21 COMB LCCOMB_X54_Y23_N18 1 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.347 ns; Loc. = LCCOMB_X54_Y23_N18; Fanout = 1; COMB Node = 'Add0~291'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~289 Add0~291 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.757 ns Add0~292 22 COMB LCCOMB_X54_Y23_N20 1 " "Info: 22: + IC(0.000 ns) + CELL(0.410 ns) = 2.757 ns; Loc. = LCCOMB_X54_Y23_N20; Fanout = 1; COMB Node = 'Add0~292'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~291 Add0~292 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.150 ns) 3.329 ns tout~176 23 COMB LCCOMB_X54_Y23_N22 1 " "Info: 23: + IC(0.422 ns) + CELL(0.150 ns) = 3.329 ns; Loc. = LCCOMB_X54_Y23_N22; Fanout = 1; COMB Node = 'tout~176'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.572 ns" { Add0~292 tout~176 } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.413 ns tout\[20\] 24 REG LCFF_X54_Y23_N23 10 " "Info: 24: + IC(0.000 ns) + CELL(0.084 ns) = 3.413 ns; Loc. = LCFF_X54_Y23_N23; Fanout = 10; REG Node = 'tout\[20\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { tout~176 tout[20] } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.658 ns ( 77.88 % ) " "Info: Total cell delay = 2.658 ns ( 77.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.755 ns ( 22.12 % ) " "Info: Total interconnect delay = 0.755 ns ( 22.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.413 ns" { tout[0] Add0~253 Add0~255 Add0~257 Add0~259 Add0~261 Add0~263 Add0~265 Add0~267 Add0~269 Add0~271 Add0~273 Add0~275 Add0~277 Add0~279 Add0~281 Add0~283 Add0~285 Add0~287 Add0~289 Add0~291 Add0~292 tout~176 tout[20] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.413 ns" { tout[0] Add0~253 Add0~255 Add0~257 Add0~259 Add0~261 Add0~263 Add0~265 Add0~267 Add0~269 Add0~271 Add0~273 Add0~275 Add0~277 Add0~279 Add0~281 Add0~283 Add0~285 Add0~287 Add0~289 Add0~291 Add0~292 tout~176 tout[20] } { 0.000ns 0.333ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.422ns 0.000ns } { 0.000ns 0.414ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.005 ns - Smallest " "Info: - Smallest clock skew is 0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M destination 2.673 ns + Shortest register " "Info: + Shortest clock path from clock \"clk50M\" to destination register is 2.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.019 ns) + CELL(0.537 ns) 2.673 ns tout\[20\] 3 REG LCFF_X54_Y23_N23 10 " "Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X54_Y23_N23; Fanout = 10; REG Node = 'tout\[20\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.556 ns" { clk50M~clkctrl tout[20] } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.46 % ) " "Info: Total cell delay = 1.536 ns ( 57.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.137 ns ( 42.54 % ) " "Info: Total interconnect delay = 1.137 ns ( 42.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clk50M clk50M~clkctrl tout[20] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clk50M clk50M~combout clk50M~clkctrl tout[20] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M source 2.668 ns - Longest register " "Info: - Longest clock path from clock \"clk50M\" to source register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns tout\[0\] 3 REG LCFF_X54_Y24_N13 3 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X54_Y24_N13; Fanout = 3; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { clk50M~clkctrl tout[0] } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk50M clk50M~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk50M clk50M~combout clk50M~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clk50M clk50M~clkctrl tout[20] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clk50M clk50M~combout clk50M~clkctrl tout[20] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk50M clk50M~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk50M clk50M~combout clk50M~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.413 ns" { tout[0] Add0~253 Add0~255 Add0~257 Add0~259 Add0~261 Add0~263 Add0~265 Add0~267 Add0~269 Add0~271 Add0~273 Add0~275 Add0~277 Add0~279 Add0~281 Add0~283 Add0~285 Add0~287 Add0~289 Add0~291 Add0~292 tout~176 tout[20] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.413 ns" { tout[0] Add0~253 Add0~255 Add0~257 Add0~259 Add0~261 Add0~263 Add0~265 Add0~267 Add0~269 Add0~271 Add0~273 Add0~275 Add0~277 Add0~279 Add0~281 Add0~283 Add0~285 Add0~287 Add0~289 Add0~291 Add0~292 tout~176 tout[20] } { 0.000ns 0.333ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.422ns 0.000ns } { 0.000ns 0.414ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clk50M clk50M~clkctrl tout[20] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clk50M clk50M~combout clk50M~clkctrl tout[20] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk50M clk50M~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk50M clk50M~combout clk50M~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk50M clk20Hz clk 6.624 ns register " "Info: tco from clock \"clk50M\" to destination pin \"clk20Hz\" through register \"clk\" is 6.624 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M source 2.675 ns + Longest register " "Info: + Longest clock path from clock \"clk50M\" to source register is 2.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk50M 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk50M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk50M~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk50M~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk50M clk50M~clkctrl } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 2.675 ns clk 3 REG LCFF_X56_Y23_N17 2 " "Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.675 ns; Loc. = LCFF_X56_Y23_N17; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.558 ns" { clk50M~clkctrl clk } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.42 % ) " "Info: Total cell delay = 1.536 ns ( 57.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.139 ns ( 42.58 % ) " "Info: Total interconnect delay = 1.139 ns ( 42.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.675 ns" { clk50M clk50M~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.675 ns" { clk50M clk50M~combout clk50M~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.699 ns + Longest register pin " "Info: + Longest register to pin delay is 3.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk 1 REG LCFF_X56_Y23_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y23_N17; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(2.612 ns) 3.699 ns clk20Hz 2 PIN PIN_L19 0 " "Info: 2: + IC(1.087 ns) + CELL(2.612 ns) = 3.699 ns; Loc. = PIN_L19; Fanout = 0; PIN Node = 'clk20Hz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.699 ns" { clk clk20Hz } "NODE_NAME" } } { "frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.612 ns ( 70.61 % ) " "Info: Total cell delay = 2.612 ns ( 70.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns ( 29.39 % ) " "Info: Total interconnect delay = 1.087 ns ( 29.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.699 ns" { clk clk20Hz } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.699 ns" { clk clk20Hz } { 0.000ns 1.087ns } { 0.000ns 2.612ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.675 ns" { clk50M clk50M~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.675 ns" { clk50M clk50M~combout clk50M~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.699 ns" { clk clk20Hz } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.699 ns" { clk clk20Hz } { 0.000ns 1.087ns } { 0.000ns 2.612ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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