frequency20hz.tan.rpt

实现交通灯控制器的vhdl编程

; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; tout[18] ; tout[4]  ; clk50M     ; clk50M   ; None                        ; None                      ; 2.052 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; tout[3]  ; tout[15] ; clk50M     ; clk50M   ; None                        ; None                      ; 2.061 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; tout[0]  ; tout[10] ; clk50M     ; clk50M   ; None                        ; None                      ; 2.043 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; tout[9]  ; tout[19] ; clk50M     ; clk50M   ; None                        ; None                      ; 2.026 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; tout[2]  ; tout[13] ; clk50M     ; clk50M   ; None                        ; None                      ; 2.023 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; tout[1]  ; tout[11] ; clk50M     ; clk50M   ; None                        ; None                      ; 2.007 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;          ;          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To      ; From Clock ;
+-------+--------------+------------+------+---------+------------+
; N/A   ; None         ; 6.624 ns   ; clk  ; clk20Hz ; clk50M     ;
+-------+--------------+------------+------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Oct 04 10:50:54 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off frequency20Hz -c frequency20Hz --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk50M" is an undefined clock
Info: Clock "clk50M" has Internal fmax of 276.09 MHz between source register "tout[0]" and destination register "tout[20]" (period= 3.622 ns)
    Info: + Longest register to register delay is 3.413 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y24_N13; Fanout = 3; REG Node = 'tout[0]'
        Info: 2: + IC(0.333 ns) + CELL(0.414 ns) = 0.747 ns; Loc. = LCCOMB_X54_Y24_N12; Fanout = 2; COMB Node = 'Add0~253'
        Info: 3: + IC(0.000 ns) + CELL(0.159 ns) = 0.906 ns; Loc. = LCCOMB_X54_Y24_N14; Fanout = 2; COMB Node = 'Add0~255'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.977 ns; Loc. = LCCOMB_X54_Y24_N16; Fanout = 2; COMB Node = 'Add0~257'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.048 ns; Loc. = LCCOMB_X54_Y24_N18; Fanout = 2; COMB Node = 'Add0~259'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.119 ns; Loc. = LCCOMB_X54_Y24_N20; Fanout = 2; COMB Node = 'Add0~261'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.190 ns; Loc. = LCCOMB_X54_Y24_N22; Fanout = 2; COMB Node = 'Add0~263'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.261 ns; Loc. = LCCOMB_X54_Y24_N24; Fanout = 2; COMB Node = 'Add0~265'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.332 ns; Loc. = LCCOMB_X54_Y24_N26; Fanout = 2; COMB Node = 'Add0~267'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.403 ns; Loc. = LCCOMB_X54_Y24_N28; Fanout = 2; COMB Node = 'Add0~269'
        Info: 11: + IC(0.000 ns) + CELL(0.146 ns) = 1.549 ns; Loc. = LCCOMB_X54_Y24_N30; Fanout = 2; COMB Node = 'Add0~271'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.620 ns; Loc. = LCCOMB_X54_Y23_N0; Fanout = 2; COMB Node = 'Add0~273'
        Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.691 ns; Loc. = LCCOMB_X54_Y23_N2; Fanout = 2; COMB Node = 'Add0~275'
        Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.762 ns; Loc. = LCCOMB_X54_Y23_N4; Fanout = 2; COMB Node = 'Add0~277'
        Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.833 ns; Loc. = LCCOMB_X54_Y23_N6; Fanout = 2; COMB Node = 'Add0~279'
        Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.904 ns; Loc. = LCCOMB_X54_Y23_N8; Fanout = 2; COMB Node = 'Add0~281'
        Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 1.975 ns; Loc. = LCCOMB_X54_Y23_N10; Fanout = 2; COMB Node = 'Add0~283'
        Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.046 ns; Loc. = LCCOMB_X54_Y23_N12; Fanout = 2; COMB Node = 'Add0~285'
        Info: 19: + IC(0.000 ns) + CELL(0.159 ns) = 2.205 ns; Loc. = LCCOMB_X54_Y23_N14; Fanout = 2; COMB Node = 'Add0~287'
        Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.276 ns; Loc. = LCCOMB_X54_Y23_N16; Fanout = 2; COMB Node = 'Add0~289'
        Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.347 ns; Loc. = LCCOMB_X54_Y23_N18; Fanout = 1; COMB Node = 'Add0~291'
        Info: 22: + IC(0.000 ns) + CELL(0.410 ns) = 2.757 ns; Loc. = LCCOMB_X54_Y23_N20; Fanout = 1; COMB Node = 'Add0~292'
        Info: 23: + IC(0.422 ns) + CELL(0.150 ns) = 3.329 ns; Loc. = LCCOMB_X54_Y23_N22; Fanout = 1; COMB Node = 'tout~176'
        Info: 24: + IC(0.000 ns) + CELL(0.084 ns) = 3.413 ns; Loc. = LCFF_X54_Y23_N23; Fanout = 10; REG Node = 'tout[20]'
        Info: Total cell delay = 2.658 ns ( 77.88 % )
        Info: Total interconnect delay = 0.755 ns ( 22.12 % )
    Info: - Smallest clock skew is 0.005 ns
        Info: + Shortest clock path from clock "clk50M" to destination register is 2.673 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk50M'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk50M~clkctrl'
            Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X54_Y23_N23; Fanout = 10; REG Node = 'tout[20]'
            Info: Total cell delay = 1.536 ns ( 57.46 % )
            Info: Total interconnect delay = 1.137 ns ( 42.54 % )
        Info: - Longest clock path from clock "clk50M" to source register is 2.668 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk50M'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk50M~clkctrl'
            Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X54_Y24_N13; Fanout = 3; REG Node = 'tout[0]'
            Info: Total cell delay = 1.536 ns ( 57.57 % )
            Info: Total interconnect delay = 1.132 ns ( 42.43 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk50M" to destination pin "clk20Hz" through register "clk" is 6.624 ns
    Info: + Longest clock path from clock "clk50M" to source register is 2.675 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk50M'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'clk50M~clkctrl'
        Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.675 ns; Loc. = LCFF_X56_Y23_N17; Fanout = 2; REG Node = 'clk'
        Info: Total cell delay = 1.536 ns ( 57.42 % )
        Info: Total interconnect delay = 1.139 ns ( 42.58 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.699 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y23_N17; Fanout = 2; REG Node = 'clk'
        Info: 2: + IC(1.087 ns) + CELL(2.612 ns) = 3.699 ns; Loc. = PIN_L19; Fanout = 0; PIN Node = 'clk20Hz'
        Info: Total cell delay = 2.612 ns ( 70.61 % )
        Info: Total interconnect delay = 1.087 ns ( 29.39 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Oct 04 10:50:55 2008
    Info: Elapsed time: 00:00:02