frequency1hz.tan.rpt

实现交通灯控制器的vhdl编程

+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From    ; To      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0] ; clk     ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 1.228 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[2] ; clk     ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[3] ; clk     ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 1.063 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[3] ; tout[1] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.993 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[1] ; clk     ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.954 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[2] ; tout[3] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.857 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[2] ; tout[1] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.857 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[1] ; tout[2] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.840 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[1] ; tout[3] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.836 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0] ; tout[2] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.568 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0] ; tout[1] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.565 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0] ; tout[3] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.564 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; clk     ; clk     ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[2] ; tout[2] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0] ; tout[0] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[3] ; tout[3] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[1] ; tout[1] ; clk20Hz    ; clk20Hz  ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To     ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A   ; None         ; 6.096 ns   ; clk  ; clk1Hz ; clk20Hz    ;
+-------+--------------+------------+------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Oct 04 11:27:03 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off frequency1Hz -c frequency1Hz --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk20Hz" is an undefined clock
Info: Clock "clk20Hz" Internal fmax is restricted to 420.17 MHz between source register "tout[0]" and destination register "clk"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.228 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y32_N23; Fanout = 5; REG Node = 'tout[0]'
            Info: 2: + IC(0.339 ns) + CELL(0.415 ns) = 0.754 ns; Loc. = LCCOMB_X1_Y32_N30; Fanout = 1; COMB Node = 'Equal0~35'
            Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 1.144 ns; Loc. = LCCOMB_X1_Y32_N20; Fanout = 1; COMB Node = 'clk~25'
            Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 1.228 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'
            Info: Total cell delay = 0.649 ns ( 52.85 % )
            Info: Total interconnect delay = 0.579 ns ( 47.15 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk20Hz" to destination register is 2.670 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk20Hz'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk20Hz~clkctrl'
                Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'
                Info: Total cell delay = 1.536 ns ( 57.53 % )
                Info: Total interconnect delay = 1.134 ns ( 42.47 % )
            Info: - Longest clock path from clock "clk20Hz" to source register is 2.670 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk20Hz'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk20Hz~clkctrl'
                Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N23; Fanout = 5; REG Node = 'tout[0]'
                Info: Total cell delay = 1.536 ns ( 57.53 % )
                Info: Total interconnect delay = 1.134 ns ( 42.47 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk20Hz" to destination pin "clk1Hz" through register "clk" is 6.096 ns
    Info: + Longest clock path from clock "clk20Hz" to source register is 2.670 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk20Hz'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk20Hz~clkctrl'
        Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'
        Info: Total cell delay = 1.536 ns ( 57.53 % )
        Info: Total interconnect delay = 1.134 ns ( 42.47 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.176 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'
        Info: 2: + IC(0.514 ns) + CELL(2.662 ns) = 3.176 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'clk1Hz'
        Info: Total cell delay = 2.662 ns ( 83.82 % )
        Info: Total interconnect delay = 0.514 ns ( 16.18 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Oct 04 11:27:04 2008
    Info: Elapsed time: 00:00:02