frequency1hz.tan.qmsg

实现交通灯控制器的vhdl编程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk20Hz register register tout\[0\] clk 420.17 MHz Internal " "Info: Clock \"clk20Hz\" Internal fmax is restricted to 420.17 MHz between source register \"tout\[0\]\" and destination register \"clk\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.228 ns + Longest register register " "Info: + Longest register to register delay is 1.228 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tout\[0\] 1 REG LCFF_X1_Y32_N23 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y32_N23; Fanout = 5; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tout[0] } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.415 ns) 0.754 ns Equal0~35 2 COMB LCCOMB_X1_Y32_N30 1 " "Info: 2: + IC(0.339 ns) + CELL(0.415 ns) = 0.754 ns; Loc. = LCCOMB_X1_Y32_N30; Fanout = 1; COMB Node = 'Equal0~35'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.754 ns" { tout[0] Equal0~35 } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(0.150 ns) 1.144 ns clk~25 3 COMB LCCOMB_X1_Y32_N20 1 " "Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 1.144 ns; Loc. = LCCOMB_X1_Y32_N20; Fanout = 1; COMB Node = 'clk~25'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.390 ns" { Equal0~35 clk~25 } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.228 ns clk 4 REG LCFF_X1_Y32_N21 2 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 1.228 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { clk~25 clk } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.649 ns ( 52.85 % ) " "Info: Total cell delay = 0.649 ns ( 52.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns ( 47.15 % ) " "Info: Total interconnect delay = 0.579 ns ( 47.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.228 ns" { tout[0] Equal0~35 clk~25 clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.228 ns" { tout[0] Equal0~35 clk~25 clk } { 0.000ns 0.339ns 0.240ns 0.000ns } { 0.000ns 0.415ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20Hz destination 2.670 ns + Shortest register " "Info: + Shortest clock path from clock \"clk20Hz\" to destination register is 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk20Hz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk20Hz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk20Hz } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk20Hz~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk20Hz~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk20Hz clk20Hz~clkctrl } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.537 ns) 2.670 ns clk 3 REG LCFF_X1_Y32_N21 2 " "Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.553 ns" { clk20Hz~clkctrl clk } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.53 % ) " "Info: Total cell delay = 1.536 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.134 ns ( 42.47 % ) " "Info: Total interconnect delay = 1.134 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20Hz source 2.670 ns - Longest register " "Info: - Longest clock path from clock \"clk20Hz\" to source register is 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk20Hz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk20Hz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk20Hz } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk20Hz~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk20Hz~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk20Hz clk20Hz~clkctrl } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.537 ns) 2.670 ns tout\[0\] 3 REG LCFF_X1_Y32_N23 5 " "Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N23; Fanout = 5; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.553 ns" { clk20Hz~clkctrl tout[0] } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.53 % ) " "Info: Total cell delay = 1.536 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.134 ns ( 42.47 % ) " "Info: Total interconnect delay = 1.134 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.228 ns" { tout[0] Equal0~35 clk~25 clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.228 ns" { tout[0] Equal0~35 clk~25 clk } { 0.000ns 0.339ns 0.240ns 0.000ns } { 0.000ns 0.415ns 0.150ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { clk } {  } {  } } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk20Hz clk1Hz clk 6.096 ns register " "Info: tco from clock \"clk20Hz\" to destination pin \"clk1Hz\" through register \"clk\" is 6.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20Hz source 2.670 ns + Longest register " "Info: + Longest clock path from clock \"clk20Hz\" to source register is 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk20Hz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk20Hz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk20Hz } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk20Hz~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk20Hz~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk20Hz clk20Hz~clkctrl } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.537 ns) 2.670 ns clk 3 REG LCFF_X1_Y32_N21 2 " "Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.553 ns" { clk20Hz~clkctrl clk } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.53 % ) " "Info: Total cell delay = 1.536 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.134 ns ( 42.47 % ) " "Info: Total interconnect delay = 1.134 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.176 ns + Longest register pin " "Info: + Longest register to pin delay is 3.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk 1 REG LCFF_X1_Y32_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y32_N21; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(2.662 ns) 3.176 ns clk1Hz 2 PIN PIN_D2 0 " "Info: 2: + IC(0.514 ns) + CELL(2.662 ns) = 3.176 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'clk1Hz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { clk clk1Hz } "NODE_NAME" } } { "frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.662 ns ( 83.82 % ) " "Info: Total cell delay = 2.662 ns ( 83.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns ( 16.18 % ) " "Info: Total interconnect delay = 0.514 ns ( 16.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { clk clk1Hz } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.176 ns" { clk clk1Hz } { 0.000ns 0.514ns } { 0.000ns 2.662ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.670 ns" { clk20Hz clk20Hz~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.670 ns" { clk20Hz clk20Hz~combout clk20Hz~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { clk clk1Hz } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.176 ns" { clk clk1Hz } { 0.000ns 0.514ns } { 0.000ns 2.662ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 04 11:27:04 2008 " "Info: Processing ended: Sat Oct 04 11:27:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}