lock.vhd

电子密码锁

library ieee;
use ieee.std_logic_1164.all;
entity lock is
port(SW : in std_logic_vector(9 downto 0);
     sel : in std_logic_vector(2 downto 0);
     HEX5,HEX4,HEX3,HEX2,HEX1,HEX0 : out std_logic_vector(6 downto 0);
     CLOCK_50 : in std_logic;
     change,test : in std_logic;
     lockopen,lockclose : out std_logic);
end entity;
architecture behav of lock is
component decoder_display is
port( clk : in std_logic;
      data : in std_logic_vector(9 downto 0);   --用于数字键0-9输入
      q : out std_logic_vector(6 downto 0);   --用于驱动数码管
      q1 : out std_logic_vector(3 downto 0)); --解码成数字，用于检测验证
end component;
component mux6_1 is
port( 
      sel : in std_logic_vector(2 downto 0);
      clk : in std_logic;
      datain : in std_logic_vector(9 downto 0);
      data0 : out std_logic_vector(9 downto 0);
      data1 : out std_logic_vector(9 downto 0);
      data2 : out std_logic_vector(9 downto 0);
      data3 : out std_logic_vector(9 downto 0);
      data4 : out std_logic_vector(9 downto 0);
      data5 : out std_logic_vector(9 downto 0));

end component;
signal enable,enable1 : std_logic;
signal temp0,temp1,temp2,temp3,temp4,temp5,deco0,deco1,deco2,deco3,deco4,deco5 : std_logic_vector(3 downto 0);
signal s0,s1,s2,s3,s4,s5 : std_logic_vector(9 downto 0);
begin
  enable<=change and (not test);
  enable1<=test and (not change);
 -- s0<="0000000000";s1<="0000000000";s2<="0000000000";s3<="0000000000";s4<="0000000000";s5<="0000000000";
u0: mux6_1 port map(sel,CLOCK_50,SW,s0,s1,s2,s3,s4,s5);
u1: decoder_display port map(clk=>CLOCK_50,data=>s0,q=>HEX0,q1=>deco0);
u2: decoder_display port map(CLOCK_50,s1,HEX1,deco1);
u3: decoder_display port map(CLOCK_50,s2,HEX2,deco2);
u4: decoder_display port map(CLOCK_50,s3,HEX3,deco3);
u5: decoder_display port map(CLOCK_50,s4,HEX4,deco4);
u6: decoder_display port map(CLOCK_50,s5,HEX5,deco5);
--process(clk)
--begin
  process(CLOCK_50,deco0,deco1,deco2,deco3,deco4,deco5)
  begin
    if rising_edge(CLOCK_50) then
      if enable='1' then
        temp0<=deco0;
        temp1<=deco1;
        temp2<=deco2;
        temp3<=deco3;
        temp4<=deco4;
        temp5<=deco5;
      end if;
      if enable1='1' then
        if temp0=deco0 and temp1=deco1 and temp2=deco2 and temp3=deco3 and temp4=deco4 and temp5=deco5 then
          lockopen<='1';
          lockclose<='0';
        else
          lockopen<='0';
          lockclose<='1';  
        end if;
      end if;
    end if;
  end process;
end behav;