lock.map.qmsg

电子密码锁

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 07 16:57:33 2008 " "Info: Processing started: Tue Oct 07 16:57:33 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lock -c lock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lock -c lock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux6_1/mux6_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mux6_1/mux6_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux6_1-behav " "Info: Found design unit 1: mux6_1-behav" {  } { { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mux6_1 " "Info: Found entity 1: mux6_1" {  } { { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lock-behav " "Info: Found design unit 1: lock-behav" {  } { { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lock " "Info: Found entity 1: lock" {  } { { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder_display/decoder_display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder_display/decoder_display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder_display-behav " "Info: Found design unit 1: decoder_display-behav" {  } { { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder_display " "Info: Found entity 1: decoder_display" {  } { { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lock " "Info: Elaborating entity \"lock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux6_1 mux6_1:u0 " "Info: Elaborating entity \"mux6_1\" for hierarchy \"mux6_1:u0\"" {  } { { "lock.vhd" "u0" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder_display decoder_display:u1 " "Info: Elaborating entity \"decoder_display\" for hierarchy \"decoder_display:u1\"" {  } { { "lock.vhd" "u1" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 39 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "lockclose~reg0 lockopen~reg0 " "Info: Duplicate register \"lockclose~reg0\" merged to single register \"lockopen~reg0\", power-up level changed" {  } { { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "380 " "Info: Implemented 380 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "16 " "Info: Implemented 16 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "44 " "Info: Implemented 44 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "320 " "Info: Implemented 320 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 07 16:57:37 2008 " "Info: Processing ended: Tue Oct 07 16:57:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}