lock.hier_info

电子密码锁

|lock
SW[0] => mux6_1:u0.datain[0]
SW[1] => mux6_1:u0.datain[1]
SW[2] => mux6_1:u0.datain[2]
SW[3] => mux6_1:u0.datain[3]
SW[4] => mux6_1:u0.datain[4]
SW[5] => mux6_1:u0.datain[5]
SW[6] => mux6_1:u0.datain[6]
SW[7] => mux6_1:u0.datain[7]
SW[8] => mux6_1:u0.datain[8]
SW[9] => mux6_1:u0.datain[9]
sel[0] => mux6_1:u0.sel[0]
sel[1] => mux6_1:u0.sel[1]
sel[2] => mux6_1:u0.sel[2]
HEX5[0] <= decoder_display:u6.q[0]
HEX5[1] <= decoder_display:u6.q[1]
HEX5[2] <= decoder_display:u6.q[2]
HEX5[3] <= decoder_display:u6.q[3]
HEX5[4] <= decoder_display:u6.q[4]
HEX5[5] <= decoder_display:u6.q[5]
HEX5[6] <= decoder_display:u6.q[6]
HEX4[0] <= decoder_display:u5.q[0]
HEX4[1] <= decoder_display:u5.q[1]
HEX4[2] <= decoder_display:u5.q[2]
HEX4[3] <= decoder_display:u5.q[3]
HEX4[4] <= decoder_display:u5.q[4]
HEX4[5] <= decoder_display:u5.q[5]
HEX4[6] <= decoder_display:u5.q[6]
HEX3[0] <= decoder_display:u4.q[0]
HEX3[1] <= decoder_display:u4.q[1]
HEX3[2] <= decoder_display:u4.q[2]
HEX3[3] <= decoder_display:u4.q[3]
HEX3[4] <= decoder_display:u4.q[4]
HEX3[5] <= decoder_display:u4.q[5]
HEX3[6] <= decoder_display:u4.q[6]
HEX2[0] <= decoder_display:u3.q[0]
HEX2[1] <= decoder_display:u3.q[1]
HEX2[2] <= decoder_display:u3.q[2]
HEX2[3] <= decoder_display:u3.q[3]
HEX2[4] <= decoder_display:u3.q[4]
HEX2[5] <= decoder_display:u3.q[5]
HEX2[6] <= decoder_display:u3.q[6]
HEX1[0] <= decoder_display:u2.q[0]
HEX1[1] <= decoder_display:u2.q[1]
HEX1[2] <= decoder_display:u2.q[2]
HEX1[3] <= decoder_display:u2.q[3]
HEX1[4] <= decoder_display:u2.q[4]
HEX1[5] <= decoder_display:u2.q[5]
HEX1[6] <= decoder_display:u2.q[6]
HEX0[0] <= decoder_display:u1.q[0]
HEX0[1] <= decoder_display:u1.q[1]
HEX0[2] <= decoder_display:u1.q[2]
HEX0[3] <= decoder_display:u1.q[3]
HEX0[4] <= decoder_display:u1.q[4]
HEX0[5] <= decoder_display:u1.q[5]
HEX0[6] <= decoder_display:u1.q[6]
CLOCK_50 => decoder_display:u6.clk
CLOCK_50 => decoder_display:u5.clk
CLOCK_50 => decoder_display:u4.clk
CLOCK_50 => decoder_display:u3.clk
CLOCK_50 => decoder_display:u2.clk
CLOCK_50 => decoder_display:u1.clk
CLOCK_50 => mux6_1:u0.clk
CLOCK_50 => lockclose~reg0.CLK
CLOCK_50 => lockopen~reg0.CLK
CLOCK_50 => temp5[0].CLK
CLOCK_50 => temp5[1].CLK
CLOCK_50 => temp5[2].CLK
CLOCK_50 => temp5[3].CLK
CLOCK_50 => temp4[0].CLK
CLOCK_50 => temp4[1].CLK
CLOCK_50 => temp4[2].CLK
CLOCK_50 => temp4[3].CLK
CLOCK_50 => temp3[0].CLK
CLOCK_50 => temp3[1].CLK
CLOCK_50 => temp3[2].CLK
CLOCK_50 => temp3[3].CLK
CLOCK_50 => temp2[0].CLK
CLOCK_50 => temp2[1].CLK
CLOCK_50 => temp2[2].CLK
CLOCK_50 => temp2[3].CLK
CLOCK_50 => temp1[0].CLK
CLOCK_50 => temp1[1].CLK
CLOCK_50 => temp1[2].CLK
CLOCK_50 => temp1[3].CLK
CLOCK_50 => temp0[0].CLK
CLOCK_50 => temp0[1].CLK
CLOCK_50 => temp0[2].CLK
CLOCK_50 => temp0[3].CLK
change => enable.IN1
change => enable1.IN1
test => enable1.IN0
test => enable.IN0
lockopen <= lockopen~reg0.DB_MAX_OUTPUT_PORT_TYPE
lockclose <= lockclose~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lock|mux6_1:u0
sel[0] => Mux0.IN4
sel[0] => Mux1.IN4
sel[0] => Mux2.IN4
sel[0] => Mux3.IN4
sel[0] => Mux4.IN4
sel[0] => Mux5.IN4
sel[0] => Mux6.IN4
sel[0] => Mux7.IN4
sel[0] => Mux8.IN4
sel[0] => Mux9.IN4
sel[0] => Mux10.IN4
sel[0] => Mux11.IN4
sel[0] => Mux12.IN4
sel[0] => Mux13.IN4
sel[0] => Mux14.IN4
sel[0] => Mux15.IN4
sel[0] => Mux16.IN4
sel[0] => Mux17.IN4
sel[0] => Mux18.IN4
sel[0] => Mux19.IN4
sel[0] => Mux20.IN4
sel[0] => Mux21.IN4
sel[0] => Mux22.IN4
sel[0] => Mux23.IN4
sel[0] => Mux24.IN4
sel[0] => Mux25.IN4
sel[0] => Mux26.IN4
sel[0] => Mux27.IN4
sel[0] => Mux28.IN4
sel[0] => Mux29.IN4
sel[0] => Mux30.IN4
sel[0] => Mux31.IN4
sel[0] => Mux32.IN4
sel[0] => Mux33.IN4
sel[0] => Mux34.IN4
sel[0] => Mux35.IN4
sel[0] => Mux36.IN4
sel[0] => Mux37.IN4
sel[0] => Mux38.IN4
sel[0] => Mux39.IN4
sel[0] => Mux40.IN4
sel[0] => Mux41.IN4
sel[0] => Mux42.IN4
sel[0] => Mux43.IN4
sel[0] => Mux44.IN4
sel[0] => Mux45.IN4
sel[0] => Mux46.IN4
sel[0] => Mux47.IN4
sel[0] => Mux48.IN4
sel[0] => Mux49.IN4
sel[0] => Mux50.IN4
sel[0] => Mux51.IN4
sel[0] => Mux52.IN4
sel[0] => Mux53.IN4
sel[0] => Mux54.IN4
sel[0] => Mux55.IN4
sel[0] => Mux56.IN4
sel[0] => Mux57.IN4
sel[0] => Mux58.IN4
sel[0] => Mux59.IN4
sel[1] => Mux0.IN3
sel[1] => Mux1.IN3
sel[1] => Mux2.IN3
sel[1] => Mux3.IN3
sel[1] => Mux4.IN3
sel[1] => Mux5.IN3
sel[1] => Mux6.IN3
sel[1] => Mux7.IN3
sel[1] => Mux8.IN3
sel[1] => Mux9.IN3
sel[1] => Mux10.IN3
sel[1] => Mux11.IN3
sel[1] => Mux12.IN3
sel[1] => Mux13.IN3
sel[1] => Mux14.IN3
sel[1] => Mux15.IN3
sel[1] => Mux16.IN3
sel[1] => Mux17.IN3
sel[1] => Mux18.IN3
sel[1] => Mux19.IN3
sel[1] => Mux20.IN3
sel[1] => Mux21.IN3
sel[1] => Mux22.IN3
sel[1] => Mux23.IN3
sel[1] => Mux24.IN3
sel[1] => Mux25.IN3
sel[1] => Mux26.IN3
sel[1] => Mux27.IN3
sel[1] => Mux28.IN3
sel[1] => Mux29.IN3
sel[1] => Mux30.IN3
sel[1] => Mux31.IN3
sel[1] => Mux32.IN3
sel[1] => Mux33.IN3
sel[1] => Mux34.IN3
sel[1] => Mux35.IN3
sel[1] => Mux36.IN3
sel[1] => Mux37.IN3
sel[1] => Mux38.IN3
sel[1] => Mux39.IN3
sel[1] => Mux40.IN3
sel[1] => Mux41.IN3
sel[1] => Mux42.IN3
sel[1] => Mux43.IN3
sel[1] => Mux44.IN3
sel[1] => Mux45.IN3
sel[1] => Mux46.IN3
sel[1] => Mux47.IN3
sel[1] => Mux48.IN3
sel[1] => Mux49.IN3
sel[1] => Mux50.IN3
sel[1] => Mux51.IN3
sel[1] => Mux52.IN3
sel[1] => Mux53.IN3
sel[1] => Mux54.IN3
sel[1] => Mux55.IN3
sel[1] => Mux56.IN3
sel[1] => Mux57.IN3
sel[1] => Mux58.IN3
sel[1] => Mux59.IN3
sel[2] => Mux0.IN2
sel[2] => Mux1.IN2
sel[2] => Mux2.IN2
sel[2] => Mux3.IN2
sel[2] => Mux4.IN2
sel[2] => Mux5.IN2
sel[2] => Mux6.IN2
sel[2] => Mux7.IN2
sel[2] => Mux8.IN2
sel[2] => Mux9.IN2
sel[2] => Mux10.IN2
sel[2] => Mux11.IN2
sel[2] => Mux12.IN2
sel[2] => Mux13.IN2
sel[2] => Mux14.IN2
sel[2] => Mux15.IN2
sel[2] => Mux16.IN2
sel[2] => Mux17.IN2
sel[2] => Mux18.IN2
sel[2] => Mux19.IN2
sel[2] => Mux20.IN2
sel[2] => Mux21.IN2
sel[2] => Mux22.IN2
sel[2] => Mux23.IN2
sel[2] => Mux24.IN2
sel[2] => Mux25.IN2
sel[2] => Mux26.IN2
sel[2] => Mux27.IN2
sel[2] => Mux28.IN2
sel[2] => Mux29.IN2
sel[2] => Mux30.IN2
sel[2] => Mux31.IN2
sel[2] => Mux32.IN2
sel[2] => Mux33.IN2
sel[2] => Mux34.IN2
sel[2] => Mux35.IN2
sel[2] => Mux36.IN2
sel[2] => Mux37.IN2
sel[2] => Mux38.IN2
sel[2] => Mux39.IN2
sel[2] => Mux40.IN2
sel[2] => Mux41.IN2
sel[2] => Mux42.IN2
sel[2] => Mux43.IN2
sel[2] => Mux44.IN2
sel[2] => Mux45.IN2
sel[2] => Mux46.IN2
sel[2] => Mux47.IN2
sel[2] => Mux48.IN2
sel[2] => Mux49.IN2
sel[2] => Mux50.IN2
sel[2] => Mux51.IN2
sel[2] => Mux52.IN2
sel[2] => Mux53.IN2
sel[2] => Mux54.IN2
sel[2] => Mux55.IN2
sel[2] => Mux56.IN2
sel[2] => Mux57.IN2
sel[2] => Mux58.IN2
sel[2] => Mux59.IN2
clk => data5[0]~reg0.CLK
clk => data5[1]~reg0.CLK
clk => data5[2]~reg0.CLK
clk => data5[3]~reg0.CLK
clk => data5[4]~reg0.CLK
clk => data5[5]~reg0.CLK
clk => data5[6]~reg0.CLK
clk => data5[7]~reg0.CLK
clk => data5[8]~reg0.CLK
clk => data5[9]~reg0.CLK
clk => data4[0]~reg0.CLK
clk => data4[1]~reg0.CLK
clk => data4[2]~reg0.CLK
clk => data4[3]~reg0.CLK
clk => data4[4]~reg0.CLK
clk => data4[5]~reg0.CLK
clk => data4[6]~reg0.CLK
clk => data4[7]~reg0.CLK
clk => data4[8]~reg0.CLK
clk => data4[9]~reg0.CLK
clk => data3[0]~reg0.CLK
clk => data3[1]~reg0.CLK
clk => data3[2]~reg0.CLK
clk => data3[3]~reg0.CLK
clk => data3[4]~reg0.CLK
clk => data3[5]~reg0.CLK
clk => data3[6]~reg0.CLK
clk => data3[7]~reg0.CLK
clk => data3[8]~reg0.CLK
clk => data3[9]~reg0.CLK
clk => data2[0]~reg0.CLK
clk => data2[1]~reg0.CLK
clk => data2[2]~reg0.CLK
clk => data2[3]~reg0.CLK
clk => data2[4]~reg0.CLK
clk => data2[5]~reg0.CLK
clk => data2[6]~reg0.CLK
clk => data2[7]~reg0.CLK
clk => data2[8]~reg0.CLK
clk => data2[9]~reg0.CLK
clk => data1[0]~reg0.CLK
clk => data1[1]~reg0.CLK
clk => data1[2]~reg0.CLK
clk => data1[3]~reg0.CLK
clk => data1[4]~reg0.CLK
clk => data1[5]~reg0.CLK
clk => data1[6]~reg0.CLK
clk => data1[7]~reg0.CLK
clk => data1[8]~reg0.CLK
clk => data1[9]~reg0.CLK
clk => data0[0]~reg0.CLK
clk => data0[1]~reg0.CLK
clk => data0[2]~reg0.CLK
clk => data0[3]~reg0.CLK
clk => data0[4]~reg0.CLK
clk => data0[5]~reg0.CLK
clk => data0[6]~reg0.CLK
clk => data0[7]~reg0.CLK
clk => data0[8]~reg0.CLK
clk => data0[9]~reg0.CLK
datain[0] => Mux9.IN5
datain[0] => Mux19.IN5
datain[0] => Mux29.IN5
datain[0] => Mux39.IN5
datain[0] => Mux49.IN5
datain[0] => Mux59.IN5
datain[1] => Mux8.IN5
datain[1] => Mux18.IN5
datain[1] => Mux28.IN5
datain[1] => Mux38.IN5
datain[1] => Mux48.IN5
datain[1] => Mux58.IN5
datain[2] => Mux7.IN5
datain[2] => Mux17.IN5
datain[2] => Mux27.IN5
datain[2] => Mux37.IN5
datain[2] => Mux47.IN5
datain[2] => Mux57.IN5
datain[3] => Mux6.IN5
datain[3] => Mux16.IN5
datain[3] => Mux26.IN5
datain[3] => Mux36.IN5
datain[3] => Mux46.IN5
datain[3] => Mux56.IN5
datain[4] => Mux5.IN5
datain[4] => Mux15.IN5
datain[4] => Mux25.IN5
datain[4] => Mux35.IN5
datain[4] => Mux45.IN5
datain[4] => Mux55.IN5
datain[5] => Mux4.IN5
datain[5] => Mux14.IN5
datain[5] => Mux24.IN5
datain[5] => Mux34.IN5
datain[5] => Mux44.IN5
datain[5] => Mux54.IN5
datain[6] => Mux3.IN5
datain[6] => Mux13.IN5
datain[6] => Mux23.IN5
datain[6] => Mux33.IN5
datain[6] => Mux43.IN5
datain[6] => Mux53.IN5
datain[7] => Mux2.IN5
datain[7] => Mux12.IN5
datain[7] => Mux22.IN5
datain[7] => Mux32.IN5
datain[7] => Mux42.IN5
datain[7] => Mux52.IN5
datain[8] => Mux1.IN5
datain[8] => Mux11.IN5
datain[8] => Mux21.IN5
datain[8] => Mux31.IN5
datain[8] => Mux41.IN5
datain[8] => Mux51.IN5
datain[9] => Mux0.IN5
datain[9] => Mux10.IN5
datain[9] => Mux20.IN5
datain[9] => Mux30.IN5
datain[9] => Mux40.IN5
datain[9] => Mux50.IN5
data0[0] <= data0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[1] <= data0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[2] <= data0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[3] <= data0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[4] <= data0[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data0[5] <= data0[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE