📄 lock.tan.qmsg

📁 电子密码锁
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register mux6_1:u0\|data4\[1\] register decoder_display:u5\|q\[0\] 189.32 MHz 5.282 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 189.32 MHz between source register \"mux6_1:u0\|data4\[1\]\" and destination register \"decoder_display:u5\|q\[0\]\" (period= 5.282 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.064 ns + Longest register register " "Info: + Longest register to register delay is 5.064 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mux6_1:u0\|data4\[1\] 1 REG LCFF_X6_Y15_N27 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y15_N27; Fanout = 5; REG Node = 'mux6_1:u0\|data4\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mux6_1:u0|data4[1] } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.323 ns) + CELL(0.376 ns) 0.699 ns decoder_display:u5\|Equal6~83 2 COMB LCCOMB_X6_Y15_N8 3 " "Info: 2: + IC(0.323 ns) + CELL(0.376 ns) = 0.699 ns; Loc. = LCCOMB_X6_Y15_N8; Fanout = 3; COMB Node = 'decoder_display:u5\|Equal6~83'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.699 ns" { mux6_1:u0|data4[1] decoder_display:u5|Equal6~83 } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.416 ns) 1.374 ns decoder_display:u5\|Equal0~71 3 COMB LCCOMB_X6_Y15_N6 3 " "Info: 3: + IC(0.259 ns) + CELL(0.416 ns) = 1.374 ns; Loc. = LCCOMB_X6_Y15_N6; Fanout = 3; COMB Node = 'decoder_display:u5\|Equal0~71'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.675 ns" { decoder_display:u5|Equal6~83 decoder_display:u5|Equal0~71 } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.275 ns) + CELL(0.438 ns) 2.087 ns decoder_display:u5\|Equal0~72 4 COMB LCCOMB_X6_Y15_N30 3 " "Info: 4: + IC(0.275 ns) + CELL(0.438 ns) = 2.087 ns; Loc. = LCCOMB_X6_Y15_N30; Fanout = 3; COMB Node = 'decoder_display:u5\|Equal0~72'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.713 ns" { decoder_display:u5|Equal0~71 decoder_display:u5|Equal0~72 } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.692 ns) + CELL(0.150 ns) 2.929 ns decoder_display:u5\|Equal0~73 5 COMB LCCOMB_X6_Y15_N24 2 " "Info: 5: + IC(0.692 ns) + CELL(0.150 ns) = 2.929 ns; Loc. = LCCOMB_X6_Y15_N24; Fanout = 2; COMB Node = 'decoder_display:u5\|Equal0~73'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.842 ns" { decoder_display:u5|Equal0~72 decoder_display:u5|Equal0~73 } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.275 ns) 3.873 ns decoder_display:u5\|WideNor0~175 6 COMB LCCOMB_X5_Y15_N30 5 " "Info: 6: + IC(0.669 ns) + CELL(0.275 ns) = 3.873 ns; Loc. = LCCOMB_X5_Y15_N30; Fanout = 5; COMB Node = 'decoder_display:u5\|WideNor0~175'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.944 ns" { decoder_display:u5|Equal0~73 decoder_display:u5|WideNor0~175 } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.687 ns) + CELL(0.420 ns) 4.980 ns decoder_display:u5\|WideOr5 7 COMB LCCOMB_X4_Y15_N12 1 " "Info: 7: + IC(0.687 ns) + CELL(0.420 ns) = 4.980 ns; Loc. = LCCOMB_X4_Y15_N12; Fanout = 1; COMB Node = 'decoder_display:u5\|WideOr5'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.107 ns" { decoder_display:u5|WideNor0~175 decoder_display:u5|WideOr5 } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.064 ns decoder_display:u5\|q\[0\] 8 REG LCFF_X4_Y15_N13 1 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 5.064 ns; Loc. = LCFF_X4_Y15_N13; Fanout = 1; REG Node = 'decoder_display:u5\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { decoder_display:u5|WideOr5 decoder_display:u5|q[0] } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.159 ns ( 42.63 % ) " "Info: Total cell delay = 2.159 ns ( 42.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.905 ns ( 57.37 % ) " "Info: Total interconnect delay = 2.905 ns ( 57.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.064 ns" { mux6_1:u0|data4[1] decoder_display:u5|Equal6~83 decoder_display:u5|Equal0~71 decoder_display:u5|Equal0~72 decoder_display:u5|Equal0~73 decoder_display:u5|WideNor0~175 decoder_display:u5|WideOr5 decoder_display:u5|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.064 ns" { mux6_1:u0|data4[1] decoder_display:u5|Equal6~83 decoder_display:u5|Equal0~71 decoder_display:u5|Equal0~72 decoder_display:u5|Equal0~73 decoder_display:u5|WideNor0~175 decoder_display:u5|WideOr5 decoder_display:u5|q[0] } { 0.000ns 0.323ns 0.259ns 0.275ns 0.692ns 0.669ns 0.687ns 0.000ns } { 0.000ns 0.376ns 0.416ns 0.438ns 0.150ns 0.275ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.677 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.677 ns decoder_display:u5\|q\[0\] 3 REG LCFF_X4_Y15_N13 1 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.677 ns; Loc. = LCFF_X4_Y15_N13; Fanout = 1; REG Node = 'decoder_display:u5\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { CLOCK_50~clkctrl decoder_display:u5|q[0] } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.38 % ) " "Info: Total cell delay = 1.536 ns ( 57.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.141 ns ( 42.62 % ) " "Info: Total interconnect delay = 1.141 ns ( 42.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { CLOCK_50 CLOCK_50~clkctrl decoder_display:u5|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl decoder_display:u5|q[0] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.681 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.681 ns mux6_1:u0\|data4\[1\] 3 REG LCFF_X6_Y15_N27 5 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X6_Y15_N27; Fanout = 5; REG Node = 'mux6_1:u0\|data4\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { CLOCK_50~clkctrl mux6_1:u0|data4[1] } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.29 % ) " "Info: Total cell delay = 1.536 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.145 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl mux6_1:u0|data4[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl mux6_1:u0|data4[1] } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { CLOCK_50 CLOCK_50~clkctrl decoder_display:u5|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl decoder_display:u5|q[0] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl mux6_1:u0|data4[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl mux6_1:u0|data4[1] } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.064 ns" { mux6_1:u0|data4[1] decoder_display:u5|Equal6~83 decoder_display:u5|Equal0~71 decoder_display:u5|Equal0~72 decoder_display:u5|Equal0~73 decoder_display:u5|WideNor0~175 decoder_display:u5|WideOr5 decoder_display:u5|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.064 ns" { mux6_1:u0|data4[1] decoder_display:u5|Equal6~83 decoder_display:u5|Equal0~71 decoder_display:u5|Equal0~72 decoder_display:u5|Equal0~73 decoder_display:u5|WideNor0~175 decoder_display:u5|WideOr5 decoder_display:u5|q[0] } { 0.000ns 0.323ns 0.259ns 0.275ns 0.692ns 0.669ns 0.687ns 0.000ns } { 0.000ns 0.376ns 0.416ns 0.438ns 0.150ns 0.275ns 0.420ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { CLOCK_50 CLOCK_50~clkctrl decoder_display:u5|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl decoder_display:u5|q[0] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl mux6_1:u0|data4[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl mux6_1:u0|data4[1] } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "mux6_1:u0\|data4\[2\] sel\[1\] CLOCK_50 8.287 ns register " "Info: tsu for register \"mux6_1:u0\|data4\[2\]\" (data pin = \"sel\[1\]\", clock pin = \"CLOCK_50\") is 8.287 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.002 ns + Longest pin register " "Info: + Longest pin to register delay is 11.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns sel\[1\] 1 PIN PIN_V1 16 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V1; Fanout = 16; PIN Node = 'sel\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sel[1] } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.304 ns) + CELL(0.275 ns) 7.431 ns mux6_1:u0\|Mux57~31 2 COMB LCCOMB_X31_Y16_N6 4 " "Info: 2: + IC(6.304 ns) + CELL(0.275 ns) = 7.431 ns; Loc. = LCCOMB_X31_Y16_N6; Fanout = 4; COMB Node = 'mux6_1:u0\|Mux57~31'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.579 ns" { sel[1] mux6_1:u0|Mux57~31 } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.205 ns) + CELL(0.366 ns) 11.002 ns mux6_1:u0\|data4\[2\] 3 REG LCFF_X5_Y15_N13 4 " "Info: 3: + IC(3.205 ns) + CELL(0.366 ns) = 11.002 ns; Loc. = LCFF_X5_Y15_N13; Fanout = 4; REG Node = 'mux6_1:u0\|data4\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.571 ns" { mux6_1:u0|Mux57~31 mux6_1:u0|data4[2] } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns ( 13.57 % ) " "Info: Total cell delay = 1.493 ns ( 13.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.509 ns ( 86.43 % ) " "Info: Total interconnect delay = 9.509 ns ( 86.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.002 ns" { sel[1] mux6_1:u0|Mux57~31 mux6_1:u0|data4[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.002 ns" { sel[1] sel[1]~combout mux6_1:u0|Mux57~31 mux6_1:u0|data4[2] } { 0.000ns 0.000ns 6.304ns 3.205ns } { 0.000ns 0.852ns 0.275ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.679 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.025 ns) + CELL(0.537 ns) 2.679 ns mux6_1:u0\|data4\[2\] 3 REG LCFF_X5_Y15_N13 4 " "Info: 3: + IC(1.025 ns) + CELL(0.537 ns) = 2.679 ns; Loc. = LCFF_X5_Y15_N13; Fanout = 4; REG Node = 'mux6_1:u0\|data4\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.562 ns" { CLOCK_50~clkctrl mux6_1:u0|data4[2] } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.33 % ) " "Info: Total cell delay = 1.536 ns ( 57.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.143 ns ( 42.67 % ) " "Info: Total interconnect delay = 1.143 ns ( 42.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl mux6_1:u0|data4[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl mux6_1:u0|data4[2] } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.002 ns" { sel[1] mux6_1:u0|Mux57~31 mux6_1:u0|data4[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.002 ns" { sel[1] sel[1]~combout mux6_1:u0|Mux57~31 mux6_1:u0|data4[2] } { 0.000ns 0.000ns 6.304ns 3.205ns } { 0.000ns 0.852ns 0.275ns 0.366ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl mux6_1:u0|data4[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl mux6_1:u0|data4[2] } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 HEX1\[0\] decoder_display:u2\|q\[0\] 9.534 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"HEX1\[0\]\" through register \"decoder_display:u2\|q\[0\]\" is 9.534 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.685 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.685 ns decoder_display:u2\|q\[0\] 3 REG LCFF_X27_Y14_N25 1 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X27_Y14_N25; Fanout = 1; REG Node = 'decoder_display:u2\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.568 ns" { CLOCK_50~clkctrl decoder_display:u2|q[0] } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { CLOCK_50 CLOCK_50~clkctrl decoder_display:u2|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl decoder_display:u2|q[0] } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.599 ns + Longest register pin " "Info: + Longest register to pin delay is 6.599 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns decoder_display:u2\|q\[0\] 1 REG LCFF_X27_Y14_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y14_N25; Fanout = 1; REG Node = 'decoder_display:u2\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { decoder_display:u2|q[0] } "NODE_NAME" } } { "decoder_display/decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.810 ns) + CELL(2.789 ns) 6.599 ns HEX1\[0\] 2 PIN PIN_V20 0 " "Info: 2: + IC(3.810 ns) + CELL(2.789 ns) = 6.599 ns; Loc. = PIN_V20; Fanout = 0; PIN Node = 'HEX1\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.599 ns" { decoder_display:u2|q[0] HEX1[0] } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.789 ns ( 42.26 % ) " "Info: Total cell delay = 2.789 ns ( 42.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.810 ns ( 57.74 % ) " "Info: Total interconnect delay = 3.810 ns ( 57.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.599 ns" { decoder_display:u2|q[0] HEX1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.599 ns" { decoder_display:u2|q[0] HEX1[0] } { 0.000ns 3.810ns } { 0.000ns 2.789ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { CLOCK_50 CLOCK_50~clkctrl decoder_display:u2|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl decoder_display:u2|q[0] } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.599 ns" { decoder_display:u2|q[0] HEX1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.599 ns" { decoder_display:u2|q[0] HEX1[0] } { 0.000ns 3.810ns } { 0.000ns 2.789ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "mux6_1:u0\|data3\[3\] SW\[3\] CLOCK_50 0.399 ns register " "Info: th for register \"mux6_1:u0\|data3\[3\]\" (data pin = \"SW\[3\]\", clock pin = \"CLOCK_50\") is 0.399 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.693 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.537 ns) 2.693 ns mux6_1:u0\|data3\[3\] 3 REG LCFF_X31_Y16_N13 4 " "Info: 3: + IC(1.039 ns) + CELL(0.537 ns) = 2.693 ns; Loc. = LCFF_X31_Y16_N13; Fanout = 4; REG Node = 'mux6_1:u0\|data3\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.576 ns" { CLOCK_50~clkctrl mux6_1:u0|data3[3] } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.04 % ) " "Info: Total cell delay = 1.536 ns ( 57.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.157 ns ( 42.96 % ) " "Info: Total interconnect delay = 1.157 ns ( 42.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl mux6_1:u0|data3[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl mux6_1:u0|data3[3] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.560 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[3\] 1 PIN PIN_AE14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 2; PIN Node = 'SW\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "lock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/lock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.327 ns) + CELL(0.150 ns) 2.476 ns mux6_1:u0\|Mux36~18 2 COMB LCCOMB_X31_Y16_N12 2 " "Info: 2: + IC(1.327 ns) + CELL(0.150 ns) = 2.476 ns; Loc. = LCCOMB_X31_Y16_N12; Fanout = 2; COMB Node = 'mux6_1:u0\|Mux36~18'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.477 ns" { SW[3] mux6_1:u0|Mux36~18 } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.560 ns mux6_1:u0\|data3\[3\] 3 REG LCFF_X31_Y16_N13 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.560 ns; Loc. = LCFF_X31_Y16_N13; Fanout = 4; REG Node = 'mux6_1:u0\|data3\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { mux6_1:u0|Mux36~18 mux6_1:u0|data3[3] } "NODE_NAME" } } { "mux6_1/mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.233 ns ( 48.16 % ) " "Info: Total cell delay = 1.233 ns ( 48.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.327 ns ( 51.84 % ) " "Info: Total interconnect delay = 1.327 ns ( 51.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.560 ns" { SW[3] mux6_1:u0|Mux36~18 mux6_1:u0|data3[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.560 ns" { SW[3] SW[3]~combout mux6_1:u0|Mux36~18 mux6_1:u0|data3[3] } { 0.000ns 0.000ns 1.327ns 0.000ns } { 0.000ns 0.999ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl mux6_1:u0|data3[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl mux6_1:u0|data3[3] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.560 ns" { SW[3] mux6_1:u0|Mux36~18 mux6_1:u0|data3[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.560 ns" { SW[3] SW[3]~combout mux6_1:u0|Mux36~18 mux6_1:u0|data3[3] } { 0.000ns 0.000ns 1.327ns 0.000ns } { 0.000ns 0.999ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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