mux6_1.tan.qmsg

电子密码锁

{ "Info" "ITDB_TSU_RESULT" "data3\[5\]~reg0 datain\[5\] clk 4.830 ns register " "Info: tsu for register \"data3\[5\]~reg0\" (data pin = \"datain\[5\]\", clock pin = \"clk\") is 4.830 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.525 ns + Longest pin register " "Info: + Longest pin to register delay is 7.525 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.822 ns) 0.822 ns datain\[5\] 1 PIN PIN_P6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_P6; Fanout = 2; PIN Node = 'datain\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { datain[5] } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.327 ns) + CELL(0.438 ns) 6.587 ns Mux24~18 2 COMB LCCOMB_X1_Y25_N18 2 " "Info: 2: + IC(5.327 ns) + CELL(0.438 ns) = 6.587 ns; Loc. = LCCOMB_X1_Y25_N18; Fanout = 2; COMB Node = 'Mux24~18'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.765 ns" { datain[5] Mux24~18 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.149 ns) 7.441 ns data3\[5\]~reg0feeder 3 COMB LCCOMB_X1_Y24_N22 1 " "Info: 3: + IC(0.705 ns) + CELL(0.149 ns) = 7.441 ns; Loc. = LCCOMB_X1_Y24_N22; Fanout = 1; COMB Node = 'data3\[5\]~reg0feeder'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.854 ns" { Mux24~18 data3[5]~reg0feeder } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.525 ns data3\[5\]~reg0 4 REG LCFF_X1_Y24_N23 1 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.525 ns; Loc. = LCFF_X1_Y24_N23; Fanout = 1; REG Node = 'data3\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { data3[5]~reg0feeder data3[5]~reg0 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns ( 19.84 % ) " "Info: Total cell delay = 1.493 ns ( 19.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.032 ns ( 80.16 % ) " "Info: Total interconnect delay = 6.032 ns ( 80.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.525 ns" { datain[5] Mux24~18 data3[5]~reg0feeder data3[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.525 ns" { datain[5] datain[5]~combout Mux24~18 data3[5]~reg0feeder data3[5]~reg0 } { 0.000ns 0.000ns 5.327ns 0.705ns 0.000ns } { 0.000ns 0.822ns 0.438ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.659 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 60 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 60; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.537 ns) 2.659 ns data3\[5\]~reg0 3 REG LCFF_X1_Y24_N23 1 " "Info: 3: + IC(1.005 ns) + CELL(0.537 ns) = 2.659 ns; Loc. = LCFF_X1_Y24_N23; Fanout = 1; REG Node = 'data3\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.542 ns" { clk~clkctrl data3[5]~reg0 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.77 % ) " "Info: Total cell delay = 1.536 ns ( 57.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.123 ns ( 42.23 % ) " "Info: Total interconnect delay = 1.123 ns ( 42.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { clk clk~clkctrl data3[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { clk clk~combout clk~clkctrl data3[5]~reg0 } { 0.000ns 0.000ns 0.118ns 1.005ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.525 ns" { datain[5] Mux24~18 data3[5]~reg0feeder data3[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.525 ns" { datain[5] datain[5]~combout Mux24~18 data3[5]~reg0feeder data3[5]~reg0 } { 0.000ns 0.000ns 5.327ns 0.705ns 0.000ns } { 0.000ns 0.822ns 0.438ns 0.149ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { clk clk~clkctrl data3[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { clk clk~combout clk~clkctrl data3[5]~reg0 } { 0.000ns 0.000ns 0.118ns 1.005ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data5\[7\] data5\[7\]~reg0 8.271 ns register " "Info: tco from clock \"clk\" to destination pin \"data5\[7\]\" through register \"data5\[7\]~reg0\" is 8.271 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.652 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 60 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 60; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.537 ns) 2.652 ns data5\[7\]~reg0 3 REG LCFF_X3_Y28_N7 1 " "Info: 3: + IC(0.998 ns) + CELL(0.537 ns) = 2.652 ns; Loc. = LCFF_X3_Y28_N7; Fanout = 1; REG Node = 'data5\[7\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.535 ns" { clk~clkctrl data5[7]~reg0 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.92 % ) " "Info: Total cell delay = 1.536 ns ( 57.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.116 ns ( 42.08 % ) " "Info: Total interconnect delay = 1.116 ns ( 42.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.652 ns" { clk clk~clkctrl data5[7]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.652 ns" { clk clk~combout clk~clkctrl data5[7]~reg0 } { 0.000ns 0.000ns 0.118ns 0.998ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.369 ns + Longest register pin " "Info: + Longest register to pin delay is 5.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data5\[7\]~reg0 1 REG LCFF_X3_Y28_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y28_N7; Fanout = 1; REG Node = 'data5\[7\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data5[7]~reg0 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.551 ns) + CELL(2.818 ns) 5.369 ns data5\[7\] 2 PIN PIN_AF5 0 " "Info: 2: + IC(2.551 ns) + CELL(2.818 ns) = 5.369 ns; Loc. = PIN_AF5; Fanout = 0; PIN Node = 'data5\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.369 ns" { data5[7]~reg0 data5[7] } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.818 ns ( 52.49 % ) " "Info: Total cell delay = 2.818 ns ( 52.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.551 ns ( 47.51 % ) " "Info: Total interconnect delay = 2.551 ns ( 47.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.369 ns" { data5[7]~reg0 data5[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.369 ns" { data5[7]~reg0 data5[7] } { 0.000ns 2.551ns } { 0.000ns 2.818ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.652 ns" { clk clk~clkctrl data5[7]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.652 ns" { clk clk~combout clk~clkctrl data5[7]~reg0 } { 0.000ns 0.000ns 0.118ns 0.998ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.369 ns" { data5[7]~reg0 data5[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.369 ns" { data5[7]~reg0 data5[7] } { 0.000ns 2.551ns } { 0.000ns 2.818ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "data0\[0\]~reg0 sel\[1\] clk -0.098 ns register " "Info: th for register \"data0\[0\]~reg0\" (data pin = \"sel\[1\]\", clock pin = \"clk\") is -0.098 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.646 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 60 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 60; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.537 ns) 2.646 ns data0\[0\]~reg0 3 REG LCFF_X1_Y28_N13 1 " "Info: 3: + IC(0.992 ns) + CELL(0.537 ns) = 2.646 ns; Loc. = LCFF_X1_Y28_N13; Fanout = 1; REG Node = 'data0\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.529 ns" { clk~clkctrl data0[0]~reg0 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.05 % ) " "Info: Total cell delay = 1.536 ns ( 58.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.110 ns ( 41.95 % ) " "Info: Total interconnect delay = 1.110 ns ( 41.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.646 ns" { clk clk~clkctrl data0[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.646 ns" { clk clk~combout clk~clkctrl data0[0]~reg0 } { 0.000ns 0.000ns 0.118ns 0.992ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.010 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.010 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns sel\[1\] 1 PIN PIN_D13 16 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 16; PIN Node = 'sel\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sel[1] } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.797 ns) + CELL(0.150 ns) 2.926 ns Mux9~31 2 COMB LCCOMB_X1_Y28_N12 4 " "Info: 2: + IC(1.797 ns) + CELL(0.150 ns) = 2.926 ns; Loc. = LCCOMB_X1_Y28_N12; Fanout = 4; COMB Node = 'Mux9~31'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.947 ns" { sel[1] Mux9~31 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.010 ns data0\[0\]~reg0 3 REG LCFF_X1_Y28_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.010 ns; Loc. = LCFF_X1_Y28_N13; Fanout = 1; REG Node = 'data0\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux9~31 data0[0]~reg0 } "NODE_NAME" } } { "mux6_1.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/mux6_1/mux6_1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 40.30 % ) " "Info: Total cell delay = 1.213 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.797 ns ( 59.70 % ) " "Info: Total interconnect delay = 1.797 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.010 ns" { sel[1] Mux9~31 data0[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.010 ns" { sel[1] sel[1]~combout Mux9~31 data0[0]~reg0 } { 0.000ns 0.000ns 1.797ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.646 ns" { clk clk~clkctrl data0[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.646 ns" { clk clk~combout clk~clkctrl data0[0]~reg0 } { 0.000ns 0.000ns 0.118ns 0.992ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.010 ns" { sel[1] Mux9~31 data0[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.010 ns" { sel[1] sel[1]~combout Mux9~31 data0[0]~reg0 } { 0.000ns 0.000ns 1.797ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 07 15:11:42 2008 " "Info: Processing ended: Tue Oct 07 15:11:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}