mux6_1.sim.rpt

电子密码锁

; |mux6_1|data2[0]~reg0       ; |mux6_1|data2[0]~reg0       ; regout           ;
; |mux6_1|data2[1]~reg0       ; |mux6_1|data2[1]~reg0       ; regout           ;
; |mux6_1|data2[2]~reg0       ; |mux6_1|data2[2]~reg0       ; regout           ;
; |mux6_1|data2[3]~reg0       ; |mux6_1|data2[3]~reg0       ; regout           ;
; |mux6_1|data2[4]~reg0       ; |mux6_1|data2[4]~reg0       ; regout           ;
; |mux6_1|data2[5]~reg0       ; |mux6_1|data2[5]~reg0       ; regout           ;
; |mux6_1|data2[6]~reg0       ; |mux6_1|data2[6]~reg0       ; regout           ;
; |mux6_1|data2[7]~reg0       ; |mux6_1|data2[7]~reg0       ; regout           ;
; |mux6_1|data2[8]~reg0       ; |mux6_1|data2[8]~reg0       ; regout           ;
; |mux6_1|data2[9]~reg0       ; |mux6_1|data2[9]~reg0       ; regout           ;
; |mux6_1|data3[0]~reg0       ; |mux6_1|data3[0]~reg0       ; regout           ;
; |mux6_1|data3[1]~reg0       ; |mux6_1|data3[1]~reg0       ; regout           ;
; |mux6_1|data3[2]~reg0       ; |mux6_1|data3[2]~reg0       ; regout           ;
; |mux6_1|data3[3]~reg0       ; |mux6_1|data3[3]~reg0       ; regout           ;
; |mux6_1|data3[4]~reg0       ; |mux6_1|data3[4]~reg0       ; regout           ;
; |mux6_1|data3[5]~reg0       ; |mux6_1|data3[5]~reg0       ; regout           ;
; |mux6_1|data3[6]~reg0       ; |mux6_1|data3[6]~reg0       ; regout           ;
; |mux6_1|data3[7]~reg0       ; |mux6_1|data3[7]~reg0       ; regout           ;
; |mux6_1|data3[8]~reg0       ; |mux6_1|data3[8]~reg0       ; regout           ;
; |mux6_1|data3[9]~reg0       ; |mux6_1|data3[9]~reg0       ; regout           ;
; |mux6_1|data4[0]~reg0       ; |mux6_1|data4[0]~reg0       ; regout           ;
; |mux6_1|data4[1]~reg0       ; |mux6_1|data4[1]~reg0       ; regout           ;
; |mux6_1|data4[2]~reg0       ; |mux6_1|data4[2]~reg0       ; regout           ;
; |mux6_1|data4[3]~reg0       ; |mux6_1|data4[3]~reg0       ; regout           ;
; |mux6_1|data4[4]~reg0       ; |mux6_1|data4[4]~reg0       ; regout           ;
; |mux6_1|data4[5]~reg0       ; |mux6_1|data4[5]~reg0       ; regout           ;
; |mux6_1|data4[6]~reg0       ; |mux6_1|data4[6]~reg0       ; regout           ;
; |mux6_1|data4[7]~reg0       ; |mux6_1|data4[7]~reg0       ; regout           ;
; |mux6_1|data4[8]~reg0       ; |mux6_1|data4[8]~reg0       ; regout           ;
; |mux6_1|data4[9]~reg0       ; |mux6_1|data4[9]~reg0       ; regout           ;
; |mux6_1|data5[0]~reg0       ; |mux6_1|data5[0]~reg0       ; regout           ;
; |mux6_1|data5[1]~reg0       ; |mux6_1|data5[1]~reg0       ; regout           ;
; |mux6_1|data5[2]~reg0       ; |mux6_1|data5[2]~reg0       ; regout           ;
; |mux6_1|data5[3]~reg0       ; |mux6_1|data5[3]~reg0       ; regout           ;
; |mux6_1|data5[4]~reg0       ; |mux6_1|data5[4]~reg0       ; regout           ;
; |mux6_1|data5[5]~reg0       ; |mux6_1|data5[5]~reg0       ; regout           ;
; |mux6_1|data5[6]~reg0       ; |mux6_1|data5[6]~reg0       ; regout           ;
; |mux6_1|data5[7]~reg0       ; |mux6_1|data5[7]~reg0       ; regout           ;
; |mux6_1|data5[8]~reg0       ; |mux6_1|data5[8]~reg0       ; regout           ;
; |mux6_1|data5[9]~reg0       ; |mux6_1|data5[9]~reg0       ; regout           ;
; |mux6_1|Mux9~31             ; |mux6_1|Mux9~31             ; combout          ;
; |mux6_1|Mux6~31             ; |mux6_1|Mux6~31             ; combout          ;
; |mux6_1|Mux4~31             ; |mux6_1|Mux4~31             ; combout          ;
; |mux6_1|Mux3~31             ; |mux6_1|Mux3~31             ; combout          ;
; |mux6_1|Mux2~31             ; |mux6_1|Mux2~31             ; combout          ;
; |mux6_1|Mux1~31             ; |mux6_1|Mux1~31             ; combout          ;
; |mux6_1|Mux29~18            ; |mux6_1|Mux29~18            ; combout          ;
; |mux6_1|Mux26~18            ; |mux6_1|Mux26~18            ; combout          ;
; |mux6_1|Mux24~18            ; |mux6_1|Mux24~18            ; combout          ;
; |mux6_1|Mux23~18            ; |mux6_1|Mux23~18            ; combout          ;
; |mux6_1|Mux22~18            ; |mux6_1|Mux22~18            ; combout          ;
; |mux6_1|Mux21~18            ; |mux6_1|Mux21~18            ; combout          ;
; |mux6_1|datain[0]           ; |mux6_1|datain[0]           ; combout          ;
; |mux6_1|datain[3]           ; |mux6_1|datain[3]           ; combout          ;
; |mux6_1|datain[5]           ; |mux6_1|datain[5]           ; combout          ;
; |mux6_1|datain[6]           ; |mux6_1|datain[6]           ; combout          ;
; |mux6_1|datain[7]           ; |mux6_1|datain[7]           ; combout          ;
; |mux6_1|datain[8]           ; |mux6_1|datain[8]           ; combout          ;
; |mux6_1|data0[0]            ; |mux6_1|data0[0]            ; padio            ;
; |mux6_1|data0[1]            ; |mux6_1|data0[1]            ; padio            ;
; |mux6_1|data0[2]            ; |mux6_1|data0[2]            ; padio            ;
; |mux6_1|data0[3]            ; |mux6_1|data0[3]            ; padio            ;
; |mux6_1|data0[5]            ; |mux6_1|data0[5]            ; padio            ;
; |mux6_1|data0[6]            ; |mux6_1|data0[6]            ; padio            ;
; |mux6_1|data0[7]            ; |mux6_1|data0[7]            ; padio            ;
; |mux6_1|data0[8]            ; |mux6_1|data0[8]            ; padio            ;
; |mux6_1|data0[9]            ; |mux6_1|data0[9]            ; padio            ;
; |mux6_1|data1[0]            ; |mux6_1|data1[0]            ; padio            ;
; |mux6_1|data1[1]            ; |mux6_1|data1[1]            ; padio            ;
; |mux6_1|data1[2]            ; |mux6_1|data1[2]            ; padio            ;
; |mux6_1|data1[3]            ; |mux6_1|data1[3]            ; padio            ;
; |mux6_1|data1[4]            ; |mux6_1|data1[4]            ; padio            ;
; |mux6_1|data1[5]            ; |mux6_1|data1[5]            ; padio            ;
; |mux6_1|data1[6]            ; |mux6_1|data1[6]            ; padio            ;
; |mux6_1|data1[7]            ; |mux6_1|data1[7]            ; padio            ;
; |mux6_1|data1[8]            ; |mux6_1|data1[8]            ; padio            ;
; |mux6_1|data1[9]            ; |mux6_1|data1[9]            ; padio            ;
; |mux6_1|data2[0]            ; |mux6_1|data2[0]            ; padio            ;
; |mux6_1|data2[1]            ; |mux6_1|data2[1]            ; padio            ;
; |mux6_1|data2[2]            ; |mux6_1|data2[2]            ; padio            ;
; |mux6_1|data2[3]            ; |mux6_1|data2[3]            ; padio            ;
; |mux6_1|data2[4]            ; |mux6_1|data2[4]            ; padio            ;
; |mux6_1|data2[5]            ; |mux6_1|data2[5]            ; padio            ;
; |mux6_1|data2[6]            ; |mux6_1|data2[6]            ; padio            ;
; |mux6_1|data2[7]            ; |mux6_1|data2[7]            ; padio            ;
; |mux6_1|data2[8]            ; |mux6_1|data2[8]            ; padio            ;
; |mux6_1|data2[9]            ; |mux6_1|data2[9]            ; padio            ;
; |mux6_1|data3[0]            ; |mux6_1|data3[0]            ; padio            ;
; |mux6_1|data3[1]            ; |mux6_1|data3[1]            ; padio            ;
; |mux6_1|data3[2]            ; |mux6_1|data3[2]            ; padio            ;
; |mux6_1|data3[3]            ; |mux6_1|data3[3]            ; padio            ;
; |mux6_1|data3[4]            ; |mux6_1|data3[4]            ; padio            ;
; |mux6_1|data3[5]            ; |mux6_1|data3[5]            ; padio            ;
; |mux6_1|data3[6]            ; |mux6_1|data3[6]            ; padio            ;
; |mux6_1|data3[7]            ; |mux6_1|data3[7]            ; padio            ;
; |mux6_1|data3[8]            ; |mux6_1|data3[8]            ; padio            ;
; |mux6_1|data3[9]            ; |mux6_1|data3[9]            ; padio            ;
; |mux6_1|data4[0]            ; |mux6_1|data4[0]            ; padio            ;
; |mux6_1|data4[1]            ; |mux6_1|data4[1]            ; padio            ;
; |mux6_1|data4[2]            ; |mux6_1|data4[2]            ; padio            ;
; |mux6_1|data4[3]            ; |mux6_1|data4[3]            ; padio            ;
; |mux6_1|data4[4]            ; |mux6_1|data4[4]            ; padio            ;
; |mux6_1|data4[5]            ; |mux6_1|data4[5]            ; padio            ;
; |mux6_1|data4[6]            ; |mux6_1|data4[6]            ; padio            ;
; |mux6_1|data4[7]            ; |mux6_1|data4[7]            ; padio            ;
; |mux6_1|data4[8]            ; |mux6_1|data4[8]            ; padio            ;
; |mux6_1|data4[9]            ; |mux6_1|data4[9]            ; padio            ;
; |mux6_1|data5[0]            ; |mux6_1|data5[0]            ; padio            ;
; |mux6_1|data5[1]            ; |mux6_1|data5[1]            ; padio            ;
; |mux6_1|data5[2]            ; |mux6_1|data5[2]            ; padio            ;
; |mux6_1|data5[3]            ; |mux6_1|data5[3]            ; padio            ;
; |mux6_1|data5[4]            ; |mux6_1|data5[4]            ; padio            ;
; |mux6_1|data5[5]            ; |mux6_1|data5[5]            ; padio            ;
; |mux6_1|data5[6]            ; |mux6_1|data5[6]            ; padio            ;
; |mux6_1|data5[7]            ; |mux6_1|data5[7]            ; padio            ;
; |mux6_1|data5[8]            ; |mux6_1|data5[8]            ; padio            ;
; |mux6_1|data5[9]            ; |mux6_1|data5[9]            ; padio            ;
; |mux6_1|data1[0]~reg0feeder ; |mux6_1|data1[0]~reg0feeder ; combout          ;
; |mux6_1|data4[0]~reg0feeder ; |mux6_1|data4[0]~reg0feeder ; combout          ;
; |mux6_1|data5[0]~reg0feeder ; |mux6_1|data5[0]~reg0feeder ; combout          ;
; |mux6_1|data1[3]~reg0feeder ; |mux6_1|data1[3]~reg0feeder ; combout          ;
; |mux6_1|data4[3]~reg0feeder ; |mux6_1|data4[3]~reg0feeder ; combout          ;
; |mux6_1|data5[5]~reg0feeder ; |mux6_1|data5[5]~reg0feeder ; combout          ;
; |mux6_1|data1[7]~reg0feeder ; |mux6_1|data1[7]~reg0feeder ; combout          ;
; |mux6_1|data4[7]~reg0feeder ; |mux6_1|data4[7]~reg0feeder ; combout          ;
; |mux6_1|data5[7]~reg0feeder ; |mux6_1|data5[7]~reg0feeder ; combout          ;
; |mux6_1|data3[5]~reg0feeder ; |mux6_1|data3[5]~reg0feeder ; combout          ;
; |mux6_1|data3[6]~reg0feeder ; |mux6_1|data3[6]~reg0feeder ; combout          ;
+-----------------------------+-----------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Oct 07 14:39:23 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off mux6_1 -c mux6_1
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      17.88 %
Info: Number of transitions in simulation is 4080
Info: Vector file mux6_1.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Oct 07 14:39:23 2008
    Info: Elapsed time: 00:00:01