decoder_display.vhd

来自「电子密码锁」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
entity decoder_display is
port( clk : in std_logic;
      data : in std_logic_vector(9 downto 0);   --用于数字键0-9输入
      q : out std_logic_vector(6 downto 0);   --用于驱动数码管
      q1 : out std_logic_vector(3 downto 0)); --解码成数字，用于检测验证
end entity;
architecture behav of decoder_display is
begin
  process(clk,data)
  begin
    if rising_edge(clk) then
      case data is
         when "0000000001" =>q<="1000000"; q1<="0000";
         when "0000000010" =>q<="1111001"; q1<="0001";
         when "0000000100" =>q<="0100100"; q1<="0010";
         when "0000001000" =>q<="0110000"; q1<="0011";
         when "0000010000" =>q<="0011001"; q1<="0100";
         when "0000100000" =>q<="0010010"; q1<="0101";
         when "0001000000" =>q<="0000010"; q1<="0110";
         when "0010000000" =>q<="1111000"; q1<="0111";
         when "0100000000" =>q<="0000000"; q1<="1000";
         when "1000000000" =>q<="0011000"; q1<="1001";
         when others=>q<="1111111";q1<="0000";
      end case;
    end if;
  end process;
end behav;