decoder_display.tan.qmsg

电子密码锁

{ "Info" "ITDB_TSU_RESULT" "q\[3\]~reg0 data\[3\] clk 9.246 ns register " "Info: tsu for register \"q\[3\]~reg0\" (data pin = \"data\[3\]\", clock pin = \"clk\") is 9.246 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.950 ns + Longest pin register " "Info: + Longest pin to register delay is 11.950 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns data\[3\] 1 PIN PIN_K22 4 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_K22; Fanout = 4; PIN Node = 'data\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data[3] } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.592 ns) + CELL(0.376 ns) 6.800 ns Equal2~84 2 COMB LCCOMB_X46_Y30_N28 3 " "Info: 2: + IC(5.592 ns) + CELL(0.376 ns) = 6.800 ns; Loc. = LCCOMB_X46_Y30_N28; Fanout = 3; COMB Node = 'Equal2~84'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.968 ns" { data[3] Equal2~84 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.420 ns) 7.487 ns Equal1~85 3 COMB LCCOMB_X46_Y30_N22 3 " "Info: 3: + IC(0.267 ns) + CELL(0.420 ns) = 7.487 ns; Loc. = LCCOMB_X46_Y30_N22; Fanout = 3; COMB Node = 'Equal1~85'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.687 ns" { Equal2~84 Equal1~85 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.420 ns) 8.356 ns Equal1~86 4 COMB LCCOMB_X47_Y30_N30 4 " "Info: 4: + IC(0.449 ns) + CELL(0.420 ns) = 8.356 ns; Loc. = LCCOMB_X47_Y30_N30; Fanout = 4; COMB Node = 'Equal1~86'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.869 ns" { Equal1~85 Equal1~86 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.150 ns) 8.954 ns Equal1~87 5 COMB LCCOMB_X46_Y30_N0 3 " "Info: 5: + IC(0.448 ns) + CELL(0.150 ns) = 8.954 ns; Loc. = LCCOMB_X46_Y30_N0; Fanout = 3; COMB Node = 'Equal1~87'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.598 ns" { Equal1~86 Equal1~87 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.242 ns) 9.652 ns WideNor0~177 6 COMB LCCOMB_X47_Y30_N24 5 " "Info: 6: + IC(0.456 ns) + CELL(0.242 ns) = 9.652 ns; Loc. = LCCOMB_X47_Y30_N24; Fanout = 5; COMB Node = 'WideNor0~177'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.698 ns" { Equal1~87 WideNor0~177 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.420 ns) 10.746 ns WideOr5~4 7 COMB LCCOMB_X47_Y30_N22 3 " "Info: 7: + IC(0.674 ns) + CELL(0.420 ns) = 10.746 ns; Loc. = LCCOMB_X47_Y30_N22; Fanout = 3; COMB Node = 'WideOr5~4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.094 ns" { WideNor0~177 WideOr5~4 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.438 ns) 11.866 ns WideOr3 8 COMB LCCOMB_X47_Y30_N6 1 " "Info: 8: + IC(0.682 ns) + CELL(0.438 ns) = 11.866 ns; Loc. = LCCOMB_X47_Y30_N6; Fanout = 1; COMB Node = 'WideOr3'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.120 ns" { WideOr5~4 WideOr3 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 11.950 ns q\[3\]~reg0 9 REG LCFF_X47_Y30_N7 1 " "Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 11.950 ns; Loc. = LCFF_X47_Y30_N7; Fanout = 1; REG Node = 'q\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { WideOr3 q[3]~reg0 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.382 ns ( 28.30 % ) " "Info: Total cell delay = 3.382 ns ( 28.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.568 ns ( 71.70 % ) " "Info: Total interconnect delay = 8.568 ns ( 71.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.950 ns" { data[3] Equal2~84 Equal1~85 Equal1~86 Equal1~87 WideNor0~177 WideOr5~4 WideOr3 q[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.950 ns" { data[3] data[3]~combout Equal2~84 Equal1~85 Equal1~86 Equal1~87 WideNor0~177 WideOr5~4 WideOr3 q[3]~reg0 } { 0.000ns 0.000ns 5.592ns 0.267ns 0.449ns 0.448ns 0.456ns 0.674ns 0.682ns 0.000ns } { 0.000ns 0.832ns 0.376ns 0.420ns 0.420ns 0.150ns 0.242ns 0.420ns 0.438ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.668 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns q\[3\]~reg0 3 REG LCFF_X47_Y30_N7 1 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X47_Y30_N7; Fanout = 1; REG Node = 'q\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { clk~clkctrl q[3]~reg0 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk clk~clkctrl q[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk clk~combout clk~clkctrl q[3]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.950 ns" { data[3] Equal2~84 Equal1~85 Equal1~86 Equal1~87 WideNor0~177 WideOr5~4 WideOr3 q[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.950 ns" { data[3] data[3]~combout Equal2~84 Equal1~85 Equal1~86 Equal1~87 WideNor0~177 WideOr5~4 WideOr3 q[3]~reg0 } { 0.000ns 0.000ns 5.592ns 0.267ns 0.449ns 0.448ns 0.456ns 0.674ns 0.682ns 0.000ns } { 0.000ns 0.832ns 0.376ns 0.420ns 0.420ns 0.150ns 0.242ns 0.420ns 0.438ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk clk~clkctrl q[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk clk~combout clk~clkctrl q[3]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[2\] q\[2\]~reg0 7.457 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[2\]\" through register \"q\[2\]~reg0\" is 7.457 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.668 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns q\[2\]~reg0 3 REG LCFF_X47_Y30_N1 1 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X47_Y30_N1; Fanout = 1; REG Node = 'q\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk clk~combout clk~clkctrl q[2]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.539 ns + Longest register pin " "Info: + Longest register to pin delay is 4.539 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[2\]~reg0 1 REG LCFF_X47_Y30_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X47_Y30_N1; Fanout = 1; REG Node = 'q\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { q[2]~reg0 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.897 ns) + CELL(2.642 ns) 4.539 ns q\[2\] 2 PIN PIN_N18 0 " "Info: 2: + IC(1.897 ns) + CELL(2.642 ns) = 4.539 ns; Loc. = PIN_N18; Fanout = 0; PIN Node = 'q\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.539 ns" { q[2]~reg0 q[2] } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 58.21 % ) " "Info: Total cell delay = 2.642 ns ( 58.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.897 ns ( 41.79 % ) " "Info: Total interconnect delay = 1.897 ns ( 41.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.539 ns" { q[2]~reg0 q[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.539 ns" { q[2]~reg0 q[2] } { 0.000ns 1.897ns } { 0.000ns 2.642ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk clk~combout clk~clkctrl q[2]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.539 ns" { q[2]~reg0 q[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.539 ns" { q[2]~reg0 q[2] } { 0.000ns 1.897ns } { 0.000ns 2.642ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q1\[3\]~reg0 data\[8\] clk 0.042 ns register " "Info: th for register \"q1\[3\]~reg0\" (data pin = \"data\[8\]\", clock pin = \"clk\") is 0.042 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.668 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns q1\[3\]~reg0 3 REG LCFF_X46_Y30_N9 1 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X46_Y30_N9; Fanout = 1; REG Node = 'q1\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { clk~clkctrl q1[3]~reg0 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk clk~clkctrl q1[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk clk~combout clk~clkctrl q1[3]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.892 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns data\[8\] 1 PIN PIN_D13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 5; PIN Node = 'data\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data[8] } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.554 ns) + CELL(0.275 ns) 2.808 ns q1~0 2 COMB LCCOMB_X46_Y30_N8 1 " "Info: 2: + IC(1.554 ns) + CELL(0.275 ns) = 2.808 ns; Loc. = LCCOMB_X46_Y30_N8; Fanout = 1; COMB Node = 'q1~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.829 ns" { data[8] q1~0 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.892 ns q1\[3\]~reg0 3 REG LCFF_X46_Y30_N9 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.892 ns; Loc. = LCFF_X46_Y30_N9; Fanout = 1; REG Node = 'q1\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { q1~0 q1[3]~reg0 } "NODE_NAME" } } { "decoder_display.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/decoder_display/decoder_display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.338 ns ( 46.27 % ) " "Info: Total cell delay = 1.338 ns ( 46.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.554 ns ( 53.73 % ) " "Info: Total interconnect delay = 1.554 ns ( 53.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.892 ns" { data[8] q1~0 q1[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.892 ns" { data[8] data[8]~combout q1~0 q1[3]~reg0 } { 0.000ns 0.000ns 1.554ns 0.000ns } { 0.000ns 0.979ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { clk clk~clkctrl q1[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.668 ns" { clk clk~combout clk~clkctrl q1[3]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.892 ns" { data[8] q1~0 q1[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.892 ns" { data[8] data[8]~combout q1~0 q1[3]~reg0 } { 0.000ns 0.000ns 1.554ns 0.000ns } { 0.000ns 0.979ns 0.275ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 07 15:12:51 2008 " "Info: Processing ended: Tue Oct 07 15:12:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}