openlock.tan.rpt

电子密码锁

; N/A           ; None        ; -0.413 ns ; change   ; temp4[0]      ; clk      ;
; N/A           ; None        ; -0.413 ns ; change   ; temp5[1]      ; clk      ;
; N/A           ; None        ; -0.413 ns ; change   ; temp1[1]      ; clk      ;
; N/A           ; None        ; -0.413 ns ; change   ; temp3[1]      ; clk      ;
; N/A           ; None        ; -0.413 ns ; change   ; temp1[0]      ; clk      ;
; N/A           ; None        ; -3.085 ns ; code0[1] ; temp0[1]      ; clk      ;
; N/A           ; None        ; -3.087 ns ; code5[2] ; temp5[2]      ; clk      ;
; N/A           ; None        ; -3.105 ns ; code3[3] ; temp3[3]      ; clk      ;
; N/A           ; None        ; -3.164 ns ; code1[0] ; temp1[0]      ; clk      ;
; N/A           ; None        ; -3.287 ns ; code2[1] ; temp2[1]      ; clk      ;
; N/A           ; None        ; -3.312 ns ; code3[2] ; temp3[2]      ; clk      ;
; N/A           ; None        ; -3.319 ns ; code5[1] ; temp5[1]      ; clk      ;
; N/A           ; None        ; -3.325 ns ; code4[0] ; temp4[0]      ; clk      ;
; N/A           ; None        ; -3.377 ns ; code1[1] ; temp1[1]      ; clk      ;
; N/A           ; None        ; -3.384 ns ; code0[0] ; temp0[0]      ; clk      ;
; N/A           ; None        ; -3.393 ns ; code5[0] ; temp5[0]      ; clk      ;
; N/A           ; None        ; -3.410 ns ; code1[3] ; temp1[3]      ; clk      ;
; N/A           ; None        ; -3.523 ns ; code0[3] ; temp0[3]      ; clk      ;
; N/A           ; None        ; -3.534 ns ; code5[3] ; temp5[3]      ; clk      ;
; N/A           ; None        ; -3.544 ns ; code3[0] ; temp3[0]      ; clk      ;
; N/A           ; None        ; -3.587 ns ; code4[3] ; temp4[3]      ; clk      ;
; N/A           ; None        ; -3.602 ns ; code2[3] ; temp2[3]      ; clk      ;
; N/A           ; None        ; -3.639 ns ; code0[2] ; temp0[2]      ; clk      ;
; N/A           ; None        ; -3.832 ns ; code4[1] ; temp4[1]      ; clk      ;
; N/A           ; None        ; -3.873 ns ; code2[0] ; temp2[0]      ; clk      ;
; N/A           ; None        ; -3.896 ns ; code2[2] ; temp2[2]      ; clk      ;
; N/A           ; None        ; -3.918 ns ; code3[1] ; temp3[1]      ; clk      ;
; N/A           ; None        ; -3.918 ns ; code4[2] ; temp4[2]      ; clk      ;
; N/A           ; None        ; -4.042 ns ; code1[2] ; temp1[2]      ; clk      ;
; N/A           ; None        ; -4.446 ns ; code3[0] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -4.517 ns ; code0[1] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -4.622 ns ; code4[3] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -4.780 ns ; code2[1] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -4.847 ns ; code5[2] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -4.952 ns ; code1[3] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.033 ns ; code1[0] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.035 ns ; code3[3] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.175 ns ; code5[1] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.225 ns ; code4[1] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.231 ns ; code4[0] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.287 ns ; code5[3] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.318 ns ; code3[2] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.408 ns ; code5[0] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.505 ns ; code2[3] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.529 ns ; code0[3] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.543 ns ; code0[0] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.609 ns ; code1[1] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.632 ns ; code2[2] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.639 ns ; code3[1] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.916 ns ; code2[0] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -5.966 ns ; code4[2] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -6.044 ns ; code1[2] ; lockopen~reg0 ; clk      ;
; N/A           ; None        ; -6.058 ns ; code0[2] ; lockopen~reg0 ; clk      ;
+---------------+-------------+-----------+----------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Oct 07 15:41:47 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off openlock -c openlock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 375.8 MHz between source register "temp4[2]" and destination register "lockopen~reg0" (period= 2.661 ns)
    Info: + Longest register to register delay is 2.447 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y35_N3; Fanout = 1; REG Node = 'temp4[2]'
        Info: 2: + IC(0.301 ns) + CELL(0.150 ns) = 0.451 ns; Loc. = LCCOMB_X28_Y35_N16; Fanout = 1; COMB Node = 'lockopen~293'
        Info: 3: + IC(0.459 ns) + CELL(0.410 ns) = 1.320 ns; Loc. = LCCOMB_X27_Y35_N14; Fanout = 1; COMB Node = 'lockopen~295'
        Info: 4: + IC(0.253 ns) + CELL(0.393 ns) = 1.966 ns; Loc. = LCCOMB_X27_Y35_N10; Fanout = 1; COMB Node = 'lockopen~305'
        Info: 5: + IC(0.247 ns) + CELL(0.150 ns) = 2.363 ns; Loc. = LCCOMB_X27_Y35_N0; Fanout = 1; COMB Node = 'lockopen~306'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.447 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
        Info: Total cell delay = 1.187 ns ( 48.51 % )
        Info: Total interconnect delay = 1.260 ns ( 51.49 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.697 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
            Info: Total cell delay = 1.536 ns ( 56.95 % )
            Info: Total interconnect delay = 1.161 ns ( 43.05 % )
        Info: - Longest clock path from clock "clk" to source register is 2.697 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X28_Y35_N3; Fanout = 1; REG Node = 'temp4[2]'
            Info: Total cell delay = 1.536 ns ( 56.95 % )
            Info: Total interconnect delay = 1.161 ns ( 43.05 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "lockopen~reg0" (data pin = "code0[2]", clock pin = "clk") is 6.288 ns
    Info: + Longest pin to register delay is 9.021 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_E5; Fanout = 2; PIN Node = 'code0[2]'
        Info: 2: + IC(5.812 ns) + CELL(0.410 ns) = 7.064 ns; Loc. = LCCOMB_X27_Y35_N20; Fanout = 1; COMB Node = 'lockopen~297'
        Info: 3: + IC(0.271 ns) + CELL(0.410 ns) = 7.745 ns; Loc. = LCCOMB_X27_Y35_N2; Fanout = 1; COMB Node = 'lockopen~300'
        Info: 4: + IC(0.248 ns) + CELL(0.150 ns) = 8.143 ns; Loc. = LCCOMB_X27_Y35_N30; Fanout = 1; COMB Node = 'lockopen~301'
        Info: 5: + IC(0.247 ns) + CELL(0.150 ns) = 8.540 ns; Loc. = LCCOMB_X27_Y35_N10; Fanout = 1; COMB Node = 'lockopen~305'
        Info: 6: + IC(0.247 ns) + CELL(0.150 ns) = 8.937 ns; Loc. = LCCOMB_X27_Y35_N0; Fanout = 1; COMB Node = 'lockopen~306'
        Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 9.021 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
        Info: Total cell delay = 2.196 ns ( 24.34 % )
        Info: Total interconnect delay = 6.825 ns ( 75.66 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.697 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
        Info: Total cell delay = 1.536 ns ( 56.95 % )
        Info: Total interconnect delay = 1.161 ns ( 43.05 % )
Info: tco from clock "clk" to destination pin "lockclose" through register "lockopen~reg0" is 8.901 ns
    Info: + Longest clock path from clock "clk" to source register is 2.697 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
        Info: Total cell delay = 1.536 ns ( 56.95 % )
        Info: Total interconnect delay = 1.161 ns ( 43.05 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.954 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
        Info: 2: + IC(3.166 ns) + CELL(2.788 ns) = 5.954 ns; Loc. = PIN_V14; Fanout = 0; PIN Node = 'lockclose'
        Info: Total cell delay = 2.788 ns ( 46.83 % )
        Info: Total interconnect delay = 3.166 ns ( 53.17 % )
Info: th for register "lockopen~reg0" (data pin = "test", clock pin = "clk") is 0.345 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.697 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
        Info: Total cell delay = 1.536 ns ( 56.95 % )
        Info: Total interconnect delay = 1.161 ns ( 43.05 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.618 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'test'
        Info: 2: + IC(1.118 ns) + CELL(0.437 ns) = 2.534 ns; Loc. = LCCOMB_X27_Y35_N0; Fanout = 1; COMB Node = 'lockopen~306'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.618 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'
        Info: Total cell delay = 1.500 ns ( 57.30 % )
        Info: Total interconnect delay = 1.118 ns ( 42.70 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Oct 07 15:41:47 2008
    Info: Elapsed time: 00:00:02