📄 openlock.tan.rpt
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Timing Analyzer report for openlock
Tue Oct 07 15:41:47 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.288 ns ; code0[2] ; lockopen~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 8.901 ns ; lockopen~reg0 ; lockopen ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.345 ns ; test ; lockopen~reg0 ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 375.80 MHz ( period = 2.661 ns ) ; temp4[2] ; lockopen~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 375.80 MHz ( period = 2.661 ns ) ; temp4[2] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.447 ns ;
; N/A ; 380.52 MHz ( period = 2.628 ns ) ; temp0[0] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.414 ns ;
; N/A ; 380.81 MHz ( period = 2.626 ns ) ; temp0[2] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.412 ns ;
; N/A ; 385.51 MHz ( period = 2.594 ns ) ; temp4[0] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.380 ns ;
; N/A ; 392.93 MHz ( period = 2.545 ns ) ; temp5[2] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.331 ns ;
; N/A ; 394.79 MHz ( period = 2.533 ns ) ; temp2[0] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.319 ns ;
; N/A ; 398.09 MHz ( period = 2.512 ns ) ; temp5[0] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.298 ns ;
; N/A ; 400.32 MHz ( period = 2.498 ns ) ; temp0[3] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.284 ns ;
; N/A ; 400.96 MHz ( period = 2.494 ns ) ; temp1[2] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.280 ns ;
; N/A ; 403.23 MHz ( period = 2.480 ns ) ; temp1[1] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.266 ns ;
; N/A ; 406.67 MHz ( period = 2.459 ns ) ; temp3[2] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.245 ns ;
; N/A ; 419.82 MHz ( period = 2.382 ns ) ; temp3[3] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.168 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp2[3] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.156 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp5[1] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.133 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp1[0] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.130 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp0[1] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.052 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp5[3] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.030 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp2[2] ; lockopen~reg0 ; clk ; clk ; None ; None ; 2.014 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp3[1] ; lockopen~reg0 ; clk ; clk ; None ; None ; 1.997 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp1[3] ; lockopen~reg0 ; clk ; clk ; None ; None ; 1.795 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp2[1] ; lockopen~reg0 ; clk ; clk ; None ; None ; 1.731 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp4[1] ; lockopen~reg0 ; clk ; clk ; None ; None ; 1.670 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp4[3] ; lockopen~reg0 ; clk ; clk ; None ; None ; 1.335 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp3[0] ; lockopen~reg0 ; clk ; clk ; None ; None ; 1.201 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; lockopen~reg0 ; lockopen~reg0 ; clk ; clk ; None ; None ; 0.407 ns ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+----------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+----------+---------------+----------+
; N/A ; None ; 6.288 ns ; code0[2] ; lockopen~reg0 ; clk ;
; N/A ; None ; 6.274 ns ; code1[2] ; lockopen~reg0 ; clk ;
; N/A ; None ; 6.196 ns ; code4[2] ; lockopen~reg0 ; clk ;
; N/A ; None ; 6.146 ns ; code2[0] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.869 ns ; code3[1] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.862 ns ; code2[2] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.839 ns ; code1[1] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.773 ns ; code0[0] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.759 ns ; code0[3] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.735 ns ; code2[3] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.638 ns ; code5[0] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.548 ns ; code3[2] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.517 ns ; code5[3] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.461 ns ; code4[0] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.455 ns ; code4[1] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.405 ns ; code5[1] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.265 ns ; code3[3] ; lockopen~reg0 ; clk ;
; N/A ; None ; 5.263 ns ; code1[0] ; lockopen~reg0 ; clk ;
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