openlock.fit.qmsg

电子密码锁

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.939 ns register register " "Info: Estimated most critical path is register to register delay of 2.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp1\[1\] 1 REG LAB_X27_Y35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y35; Fanout = 1; REG Node = 'temp1\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp1[1] } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.185 ns) + CELL(0.410 ns) 0.595 ns lockopen~299 2 COMB LAB_X27_Y35 1 " "Info: 2: + IC(0.185 ns) + CELL(0.410 ns) = 0.595 ns; Loc. = LAB_X27_Y35; Fanout = 1; COMB Node = 'lockopen~299'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.595 ns" { temp1[1] lockopen~299 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 1.160 ns lockopen~300 3 COMB LAB_X27_Y35 1 " "Info: 3: + IC(0.415 ns) + CELL(0.150 ns) = 1.160 ns; Loc. = LAB_X27_Y35; Fanout = 1; COMB Node = 'lockopen~300'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { lockopen~299 lockopen~300 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 1.725 ns lockopen~301 4 COMB LAB_X27_Y35 1 " "Info: 4: + IC(0.127 ns) + CELL(0.438 ns) = 1.725 ns; Loc. = LAB_X27_Y35; Fanout = 1; COMB Node = 'lockopen~301'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { lockopen~300 lockopen~301 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 2.290 ns lockopen~305 5 COMB LAB_X27_Y35 1 " "Info: 5: + IC(0.290 ns) + CELL(0.275 ns) = 2.290 ns; Loc. = LAB_X27_Y35; Fanout = 1; COMB Node = 'lockopen~305'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { lockopen~301 lockopen~305 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 2.855 ns lockopen~306 6 COMB LAB_X27_Y35 1 " "Info: 6: + IC(0.415 ns) + CELL(0.150 ns) = 2.855 ns; Loc. = LAB_X27_Y35; Fanout = 1; COMB Node = 'lockopen~306'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { lockopen~305 lockopen~306 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.939 ns lockopen~reg0 7 REG LAB_X27_Y35 3 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 2.939 ns; Loc. = LAB_X27_Y35; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.507 ns ( 51.28 % ) " "Info: Total cell delay = 1.507 ns ( 51.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.432 ns ( 48.72 % ) " "Info: Total interconnect delay = 1.432 ns ( 48.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.939 ns" { temp1[1] lockopen~299 lockopen~300 lockopen~301 lockopen~305 lockopen~306 lockopen~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x22_y24 x32_y36 " "Info: The peak interconnect region extends from location x22_y24 to location x32_y36" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "2 " "Warning: Found 2 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "lockopen 0 " "Info: Pin \"lockopen\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "lockclose 0 " "Info: Pin \"lockclose\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 07 15:41:28 2008 " "Info: Processing ended: Tue Oct 07 15:41:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.fit.smsg " "Info: Generated suppressed messages file E:/SOPClab/digital_system_design/password_lock/openlock/openlock.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}