prev_cmp_p2r_cordic.qmsg

一个很不错的cordic利用流水线计算正余弦的程序

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "p2r_CordicPipe:\\gen_pipe:10:Pipe\|Zo\[0\] data_in GND " "Warning (14130): Reduced register \"p2r_CordicPipe:\\gen_pipe:10:Pipe\|Zo\[0\]\" with stuck data_in port to stuck value GND" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "p2r_CordicPipe:\\gen_pipe:11:Pipe\|Zo\[0\] High " "Info: Power-up level of register \"p2r_CordicPipe:\\gen_pipe:11:Pipe\|Zo\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "p2r_CordicPipe:\\gen_pipe:11:Pipe\|Zo\[0\] data_in VCC " "Warning (14130): Reduced register \"p2r_CordicPipe:\\gen_pipe:11:Pipe\|Zo\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "p2r_CordicPipe:\\gen_pipe:12:Pipe\|Zo\[0\] data_in GND " "Warning (14130): Reduced register \"p2r_CordicPipe:\\gen_pipe:12:Pipe\|Zo\[0\]\" with stuck data_in port to stuck value GND" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "p2r_CordicPipe:\\gen_pipe:13:Pipe\|Zo\[0\] High " "Info: Power-up level of register \"p2r_CordicPipe:\\gen_pipe:13:Pipe\|Zo\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "p2r_CordicPipe:\\gen_pipe:13:Pipe\|Zo\[0\] data_in VCC " "Warning (14130): Reduced register \"p2r_CordicPipe:\\gen_pipe:13:Pipe\|Zo\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[1\] p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[2\] " "Info: Duplicate register \"p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[1\]\" merged to single register \"p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[2\]\", power-up level changed" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "p2r_CordicPipe:\\gen_pipe:1:Pipe\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"p2r_CordicPipe:\\gen_pipe:1:Pipe\|Add0\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "Add0" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "p2r_CordicPipe:\\gen_pipe:1:Pipe\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"p2r_CordicPipe:\\gen_pipe:1:Pipe\|Add0\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "Add0" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../../../altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../../../../altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "p2r_CordicPipe:\\gen_pipe:1:Pipe\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"p2r_CordicPipe:\\gen_pipe:1:Pipe\|lpm_add_sub:Add0\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qjg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qjg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qjg " "Info: Found entity 1: add_sub_qjg" {  } { { "db/add_sub_qjg.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/db/add_sub_qjg.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1300 " "Info: Implemented 1300 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "50 " "Info: Implemented 50 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "1218 " "Info: Implemented 1218 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 23 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "166 " "Info: Allocated 166 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 01 16:40:40 2008 " "Info: Processing ended: Tue Jul 01 16:40:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}