p2r_cordic.tan.qmsg

一个很不错的cordic利用流水线计算正余弦的程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk Yo\[1\] p2r_CordicPipe:\\gen_pipe:15:Pipe\|Yo\[1\] 11.073 ns register " "Info: tco from clock \"clk\" to destination pin \"Yo\[1\]\" through register \"p2r_CordicPipe:\\gen_pipe:15:Pipe\|Yo\[1\]\" is 11.073 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.203 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.203 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G3 719 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 719; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.208 ns) + CELL(0.666 ns) 3.203 ns p2r_CordicPipe:\\gen_pipe:15:Pipe\|Yo\[1\] 3 REG LCFF_X28_Y21_N21 1 " "Info: 3: + IC(1.208 ns) + CELL(0.666 ns) = 3.203 ns; Loc. = LCFF_X28_Y21_N21; Fanout = 1; REG Node = 'p2r_CordicPipe:\\gen_pipe:15:Pipe\|Yo\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.874 ns" { clk~clkctrl p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 54.82 % ) " "Info: Total cell delay = 1.756 ns ( 54.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.447 ns ( 45.18 % ) " "Info: Total interconnect delay = 1.447 ns ( 45.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.203 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.203 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] {} } { 0.000ns 0.000ns 0.239ns 1.208ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.566 ns + Longest register pin " "Info: + Longest register to pin delay is 7.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns p2r_CordicPipe:\\gen_pipe:15:Pipe\|Yo\[1\] 1 REG LCFF_X28_Y21_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y21_N21; Fanout = 1; REG Node = 'p2r_CordicPipe:\\gen_pipe:15:Pipe\|Yo\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.540 ns) + CELL(3.026 ns) 7.566 ns Yo\[1\] 2 PIN PIN_L8 0 " "Info: 2: + IC(4.540 ns) + CELL(3.026 ns) = 7.566 ns; Loc. = PIN_L8; Fanout = 0; PIN Node = 'Yo\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.566 ns" { p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] Yo[1] } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.026 ns ( 39.99 % ) " "Info: Total cell delay = 3.026 ns ( 39.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.540 ns ( 60.01 % ) " "Info: Total interconnect delay = 4.540 ns ( 60.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.566 ns" { p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] Yo[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.566 ns" { p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] {} Yo[1] {} } { 0.000ns 4.540ns } { 0.000ns 3.026ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.203 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.203 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] {} } { 0.000ns 0.000ns 0.239ns 1.208ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.566 ns" { p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] Yo[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.566 ns" { p2r_CordicPipe:\gen_pipe:15:Pipe|Yo[1] {} Yo[1] {} } { 0.000ns 4.540ns } { 0.000ns 3.026ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\] Yi\[6\] clk -1.428 ns register " "Info: th for register \"p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\]\" (data pin = \"Yi\[6\]\", clock pin = \"clk\") is -1.428 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.208 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G3 719 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 719; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.666 ns) 3.208 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\] 3 REG LCFF_X30_Y18_N9 3 " "Info: 3: + IC(1.213 ns) + CELL(0.666 ns) = 3.208 ns; Loc. = LCFF_X30_Y18_N9; Fanout = 3; REG Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.879 ns" { clk~clkctrl p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 54.74 % ) " "Info: Total cell delay = 1.756 ns ( 54.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.452 ns ( 45.26 % ) " "Info: Total interconnect delay = 1.452 ns ( 45.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.208 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.208 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11] {} } { 0.000ns 0.000ns 0.239ns 1.213ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.942 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns Yi\[6\] 1 PIN PIN_U11 3 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_U11; Fanout = 3; PIN Node = 'Yi\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Yi[6] } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.189 ns) + CELL(0.705 ns) 3.984 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[6\]~133 2 COMB LCCOMB_X30_Y19_N30 2 " "Info: 2: + IC(2.189 ns) + CELL(0.705 ns) = 3.984 ns; Loc. = LCCOMB_X30_Y19_N30; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[6\]~133'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { Yi[6] p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[6]~133 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.070 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[7\]~135 3 COMB LCCOMB_X30_Y18_N0 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 4.070 ns; Loc. = LCCOMB_X30_Y18_N0; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[7\]~135'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[6]~133 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[7]~135 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.156 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[8\]~137 4 COMB LCCOMB_X30_Y18_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 4.156 ns; Loc. = LCCOMB_X30_Y18_N2; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[8\]~137'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[7]~135 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[8]~137 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.242 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[9\]~139 5 COMB LCCOMB_X30_Y18_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 4.242 ns; Loc. = LCCOMB_X30_Y18_N4; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[9\]~139'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[8]~137 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[9]~139 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.328 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[10\]~141 6 COMB LCCOMB_X30_Y18_N6 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 4.328 ns; Loc. = LCCOMB_X30_Y18_N6; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[10\]~141'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[9]~139 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[10]~141 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.834 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\]~142 7 COMB LCCOMB_X30_Y18_N8 1 " "Info: 7: + IC(0.000 ns) + CELL(0.506 ns) = 4.834 ns; Loc. = LCCOMB_X30_Y18_N8; Fanout = 1; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\]~142'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[10]~141 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11]~142 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.942 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\] 8 REG LCFF_X30_Y18_N9 3 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 4.942 ns; Loc. = LCFF_X30_Y18_N9; Fanout = 3; REG Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Yo\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11]~142 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.753 ns ( 55.71 % ) " "Info: Total cell delay = 2.753 ns ( 55.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.189 ns ( 44.29 % ) " "Info: Total interconnect delay = 2.189 ns ( 44.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.942 ns" { Yi[6] p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[6]~133 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[7]~135 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[8]~137 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[9]~139 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[10]~141 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11]~142 p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.942 ns" { Yi[6] {} Yi[6]~combout {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[6]~133 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[7]~135 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[8]~137 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[9]~139 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[10]~141 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11]~142 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Yo[11] {} } { 0.000ns 0.000ns 2.189ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.090ns 0.705ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.f