📄 p2r_cordic.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[19\] register p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\] 142.73 MHz 7.006 ns Internal " "Info: Clock \"clk\" has Internal fmax of 142.73 MHz between source register \"p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[19\]\" and destination register \"p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\]\" (period= 7.006 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.729 ns + Longest register register " "Info: + Longest register to register delay is 6.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[19\] 1 REG LCFF_X20_Y20_N31 60 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y20_N31; Fanout = 60; REG Node = 'p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[19\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.633 ns) + CELL(0.370 ns) 3.003 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Add2~363 2 COMB LCCOMB_X36_Y21_N0 2 " "Info: 2: + IC(2.633 ns) + CELL(0.370 ns) = 3.003 ns; Loc. = LCCOMB_X36_Y21_N0; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Add2~363'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.003 ns" { p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] p2r_CordicPipe:\gen_pipe:5:Pipe|Add2~363 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.621 ns) 4.718 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[0\]~119 3 COMB LCCOMB_X35_Y20_N18 2 " "Info: 3: + IC(1.094 ns) + CELL(0.621 ns) = 4.718 ns; Loc. = LCCOMB_X35_Y20_N18; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[0\]~119'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.715 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Add2~363 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[0]~119 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.804 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[1\]~121 4 COMB LCCOMB_X35_Y20_N20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 4.804 ns; Loc. = LCCOMB_X35_Y20_N20; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[1\]~121'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[0]~119 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[1]~121 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.890 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[2\]~123 5 COMB LCCOMB_X35_Y20_N22 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 4.890 ns; Loc. = LCCOMB_X35_Y20_N22; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[2\]~123'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[1]~121 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[2]~123 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.976 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[3\]~125 6 COMB LCCOMB_X35_Y20_N24 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 4.976 ns; Loc. = LCCOMB_X35_Y20_N24; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[3\]~125'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[2]~123 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[3]~125 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.062 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[4\]~127 7 COMB LCCOMB_X35_Y20_N26 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 5.062 ns; Loc. = LCCOMB_X35_Y20_N26; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[4\]~127'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[3]~125 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[4]~127 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.148 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[5\]~129 8 COMB LCCOMB_X35_Y20_N28 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 5.148 ns; Loc. = LCCOMB_X35_Y20_N28; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[5\]~129'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[4]~127 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[5]~129 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 5.323 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[6\]~131 9 COMB LCCOMB_X35_Y20_N30 2 " "Info: 9: + IC(0.000 ns) + CELL(0.175 ns) = 5.323 ns; Loc. = LCCOMB_X35_Y20_N30; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[6\]~131'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[5]~129 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[6]~131 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.409 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[7\]~133 10 COMB LCCOMB_X35_Y19_N0 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 5.409 ns; Loc. = LCCOMB_X35_Y19_N0; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[7\]~133'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[6]~131 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[7]~133 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.495 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[8\]~135 11 COMB LCCOMB_X35_Y19_N2 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 5.495 ns; Loc. = LCCOMB_X35_Y19_N2; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[8\]~135'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[7]~133 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[8]~135 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.581 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[9\]~137 12 COMB LCCOMB_X35_Y19_N4 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 5.581 ns; Loc. = LCCOMB_X35_Y19_N4; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[9\]~137'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[8]~135 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[9]~137 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.667 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[10\]~139 13 COMB LCCOMB_X35_Y19_N6 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 5.667 ns; Loc. = LCCOMB_X35_Y19_N6; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[10\]~139'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[9]~137 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[10]~139 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.753 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[11\]~141 14 COMB LCCOMB_X35_Y19_N8 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 5.753 ns; Loc. = LCCOMB_X35_Y19_N8; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[11\]~141'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[10]~139 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[11]~141 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.839 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[12\]~143 15 COMB LCCOMB_X35_Y19_N10 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 5.839 ns; Loc. = LCCOMB_X35_Y19_N10; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[12\]~143'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[11]~141 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[12]~143 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.925 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[13\]~145 16 COMB LCCOMB_X35_Y19_N12 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 5.925 ns; Loc. = LCCOMB_X35_Y19_N12; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[13\]~145'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[12]~143 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[13]~145 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 6.115 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[14\]~147 17 COMB LCCOMB_X35_Y19_N14 1 " "Info: 17: + IC(0.000 ns) + CELL(0.190 ns) = 6.115 ns; Loc. = LCCOMB_X35_Y19_N14; Fanout = 1; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[14\]~147'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[13]~145 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[14]~147 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 6.621 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\]~148 18 COMB LCCOMB_X35_Y19_N16 1 " "Info: 18: + IC(0.000 ns) + CELL(0.506 ns) = 6.621 ns; Loc. = LCCOMB_X35_Y19_N16; Fanout = 1; COMB Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\]~148'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[14]~147 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15]~148 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.729 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\] 19 REG LCFF_X35_Y19_N17 2 " "Info: 19: + IC(0.000 ns) + CELL(0.108 ns) = 6.729 ns; Loc. = LCFF_X35_Y19_N17; Fanout = 2; REG Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15]~148 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.002 ns ( 44.61 % ) " "Info: Total cell delay = 3.002 ns ( 44.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.727 ns ( 55.39 % ) " "Info: Total interconnect delay = 3.727 ns ( 55.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.729 ns" { p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] p2r_CordicPipe:\gen_pipe:5:Pipe|Add2~363 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[0]~119 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[1]~121 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[2]~123 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[3]~125 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[4]~127 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[5]~129 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[6]~131 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[7]~133 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[8]~135 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[9]~137 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[10]~139 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[11]~141 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[12]~143 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[13]~145 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[14]~147 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15]~148 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.729 ns" { p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] {} p2r_CordicPipe:\gen_pipe:5:Pipe|Add2~363 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[0]~119 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[1]~121 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[2]~123 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[3]~125 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[4]~127 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[5]~129 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[6]~131 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[7]~133 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[8]~135 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[9]~137 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[10]~139 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[11]~141 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[12]~143 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[13]~145 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[14]~147 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15]~148 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] {} } { 0.000ns 2.633ns 1.094ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.370ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.506ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.013 ns - Smallest " "Info: - Smallest clock skew is -0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.183 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.183 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G3 719 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 719; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(0.666 ns) 3.183 ns p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\] 3 REG LCFF_X35_Y19_N17 2 " "Info: 3: + IC(1.188 ns) + CELL(0.666 ns) = 3.183 ns; Loc. = LCFF_X35_Y19_N17; Fanout = 2; REG Node = 'p2r_CordicPipe:\\gen_pipe:5:Pipe\|Yo\[15\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.854 ns" { clk~clkctrl p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.17 % ) " "Info: Total cell delay = 1.756 ns ( 55.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.427 ns ( 44.83 % ) " "Info: Total interconnect delay = 1.427 ns ( 44.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.183 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.183 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] {} } { 0.000ns 0.000ns 0.239ns 1.188ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.196 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G3 719 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 719; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.666 ns) 3.196 ns p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[19\] 3 REG LCFF_X20_Y20_N31 60 " "Info: 3: + IC(1.201 ns) + CELL(0.666 ns) = 3.196 ns; Loc. = LCFF_X20_Y20_N31; Fanout = 60; REG Node = 'p2r_CordicPipe:\\gen_pipe:4:Pipe\|Zo\[19\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.867 ns" { clk~clkctrl p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 54.94 % ) " "Info: Total cell delay = 1.756 ns ( 54.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.440 ns ( 45.06 % ) " "Info: Total interconnect delay = 1.440 ns ( 45.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.196 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.196 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] {} } { 0.000ns 0.000ns 0.239ns 1.201ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.183 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.183 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] {} } { 0.000ns 0.000ns 0.239ns 1.188ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.196 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.196 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] {} } { 0.000ns 0.000ns 0.239ns 1.201ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.729 ns" { p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] p2r_CordicPipe:\gen_pipe:5:Pipe|Add2~363 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[0]~119 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[1]~121 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[2]~123 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[3]~125 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[4]~127 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[5]~129 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[6]~131 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[7]~133 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[8]~135 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[9]~137 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[10]~139 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[11]~141 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[12]~143 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[13]~145 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[14]~147 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15]~148 p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.729 ns" { p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] {} p2r_CordicPipe:\gen_pipe:5:Pipe|Add2~363 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[0]~119 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[1]~121 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[2]~123 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[3]~125 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[4]~127 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[5]~129 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[6]~131 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[7]~133 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[8]~135 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[9]~137 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[10]~139 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[11]~141 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[12]~143 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[13]~145 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[14]~147 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15]~148 {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] {} } { 0.000ns 2.633ns 1.094ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.370ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.506ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.183 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.183 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:5:Pipe|Yo[15] {} } { 0.000ns 0.000ns 0.239ns 1.188ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.196 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.196 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:4:Pipe|Zo[19] {} } { 0.000ns 0.000ns 0.239ns 1.201ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\] Zi\[15\] clk 10.660 ns register " "Info: tsu for register \"p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\]\" (data pin = \"Zi\[15\]\", clock pin = \"clk\") is 10.660 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.905 ns + Longest pin register " "Info: + Longest pin to register delay is 13.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns Zi\[15\] 1 PIN PIN_AB9 38 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_AB9; Fanout = 38; PIN Node = 'Zi\[15\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Zi[15] } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.480 ns) + CELL(0.651 ns) 9.055 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|lpm_add_sub:Add0\|add_sub_qjg:auto_generated\|_~13 2 COMB LCCOMB_X30_Y19_N12 2 " "Info: 2: + IC(7.480 ns) + CELL(0.651 ns) = 9.055 ns; Loc. = LCCOMB_X30_Y19_N12; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|lpm_add_sub:Add0\|add_sub_qjg:auto_generated\|_~13'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.131 ns" { Zi[15] p2r_CordicPipe:\gen_pipe:1:Pipe|lpm_add_sub:Add0|add_sub_qjg:auto_generated|_~13 } "NODE_NAME" } } { "lpm_add_sub.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.621 ns) 10.794 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[4\]~129 3 COMB LCCOMB_X29_Y19_N26 2 " "Info: 3: + IC(1.118 ns) + CELL(0.621 ns) = 10.794 ns; Loc. = LCCOMB_X29_Y19_N26; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[4\]~129'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.739 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|lpm_add_sub:Add0|add_sub_qjg:auto_generated|_~13 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[4]~129 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 10.880 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[5\]~131 4 COMB LCCOMB_X29_Y19_N28 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 10.880 ns; Loc. = LCCOMB_X29_Y19_N28; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[5\]~131'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[4]~129 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[5]~131 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 11.055 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[6\]~133 5 COMB LCCOMB_X29_Y19_N30 2 " "Info: 5: + IC(0.000 ns) + CELL(0.175 ns) = 11.055 ns; Loc. = LCCOMB_X29_Y19_N30; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[6\]~133'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[5]~131 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[6]~133 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 11.141 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[7\]~135 6 COMB LCCOMB_X29_Y18_N0 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 11.141 ns; Loc. = LCCOMB_X29_Y18_N0; Fanout = 2; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[7\]~135'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[6]~133 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[7]~135 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 11.647 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\]~136 7 COMB LCCOMB_X29_Y18_N2 1 " "Info: 7: + IC(0.000 ns) + CELL(0.506 ns) = 11.647 ns; Loc. = LCCOMB_X29_Y18_N2; Fanout = 1; COMB Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\]~136'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[7]~135 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8]~136 } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.798 ns) + CELL(0.460 ns) 13.905 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\] 8 REG LCFF_X28_Y20_N27 3 " "Info: 8: + IC(1.798 ns) + CELL(0.460 ns) = 13.905 ns; Loc. = LCFF_X28_Y20_N27; Fanout = 3; REG Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.258 ns" { p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8]~136 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.509 ns ( 25.24 % ) " "Info: Total cell delay = 3.509 ns ( 25.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.396 ns ( 74.76 % ) " "Info: Total interconnect delay = 10.396 ns ( 74.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.905 ns" { Zi[15] p2r_CordicPipe:\gen_pipe:1:Pipe|lpm_add_sub:Add0|add_sub_qjg:auto_generated|_~13 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[4]~129 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[5]~131 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[6]~133 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[7]~135 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8]~136 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.905 ns" { Zi[15] {} Zi[15]~combout {} p2r_CordicPipe:\gen_pipe:1:Pipe|lpm_add_sub:Add0|add_sub_qjg:auto_generated|_~13 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[4]~129 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[5]~131 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[6]~133 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[7]~135 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8]~136 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] {} } { 0.000ns 0.000ns 7.480ns 1.118ns 0.000ns 0.000ns 0.000ns 0.000ns 1.798ns } { 0.000ns 0.924ns 0.651ns 0.621ns 0.086ns 0.175ns 0.086ns 0.506ns 0.460ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.205 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.205 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G3 719 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 719; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "p2r_cordic.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_cordic.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.210 ns) + CELL(0.666 ns) 3.205 ns p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\] 3 REG LCFF_X28_Y20_N27 3 " "Info: 3: + IC(1.210 ns) + CELL(0.666 ns) = 3.205 ns; Loc. = LCFF_X28_Y20_N27; Fanout = 3; REG Node = 'p2r_CordicPipe:\\gen_pipe:1:Pipe\|Xo\[8\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { clk~clkctrl p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] } "NODE_NAME" } } { "p2r_CordicPipe.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/Cordic算法的VHDL实现/Cordic算法的VHDL实现/cordic/cordic/polar2rect/p2r_CordicPipe.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 54.79 % ) " "Info: Total cell delay = 1.756 ns ( 54.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.449 ns ( 45.21 % ) " "Info: Total interconnect delay = 1.449 ns ( 45.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.205 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.205 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] {} } { 0.000ns 0.000ns 0.239ns 1.210ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.905 ns" { Zi[15] p2r_CordicPipe:\gen_pipe:1:Pipe|lpm_add_sub:Add0|add_sub_qjg:auto_generated|_~13 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[4]~129 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[5]~131 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[6]~133 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[7]~135 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8]~136 p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.905 ns" { Zi[15] {} Zi[15]~combout {} p2r_CordicPipe:\gen_pipe:1:Pipe|lpm_add_sub:Add0|add_sub_qjg:auto_generated|_~13 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[4]~129 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[5]~131 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[6]~133 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[7]~135 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8]~136 {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] {} } { 0.000ns 0.000ns 7.480ns 1.118ns 0.000ns 0.000ns 0.000ns 0.000ns 1.798ns } { 0.000ns 0.924ns 0.651ns 0.621ns 0.086ns 0.175ns 0.086ns 0.506ns 0.460ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.205 ns" { clk clk~clkctrl p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.205 ns" { clk {} clk~combout {} clk~clkctrl {} p2r_CordicPipe:\gen_pipe:1:Pipe|Xo[8] {} } { 0.000ns 0.000ns 0.239ns 1.210ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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