seg71.tan.qmsg

几个常用的接口实验的程序代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:cnt_scan_rtl_0\|dffs\[0\] register lpm_counter:cnt_scan_rtl_0\|dffs\[15\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"lpm_counter:cnt_scan_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:cnt_scan_rtl_0\|dffs\[15\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[0\] 1 REG LC1 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "" { lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[15\] 2 REG LC81 21 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC81; Fanout = 21; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[15\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "" { clk } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[15\] 2 REG LC81 21 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC81; Fanout = 21; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[15\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "0.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "" { clk } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[0\] 2 REG LC1 16 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "0.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[4\] lpm_counter:cnt_scan_rtl_0\|dffs\[13\] 17.000 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[4\]\" through register \"lpm_counter:cnt_scan_rtl_0\|dffs\[13\]\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "" { clk } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[13\] 2 REG LC83 23 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC83; Fanout = 23; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[13\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "0.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[13] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[13\] 1 REG LC83 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC83; Fanout = 23; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[13\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "" { lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns reduce_or~388 2 COMB LC93 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'reduce_or~388'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "9.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] reduce_or~388 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns dataout\[4\] 3 PIN PIN_60 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'dataout\[4\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "4.000 ns" { reduce_or~388 dataout[4] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "13.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] reduce_or~388 dataout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] reduce_or~388 dataout[4] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[13] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71_cmp.qrpt" Compiler "seg71" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/" "" "13.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] reduce_or~388 dataout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] reduce_or~388 dataout[4] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 11:12:48 2005 " "Info: Processing ended: Wed Dec 14 11:12:48 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}