seg71.map.qmsg

几个常用的接口实验的程序代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 11:12:41 2005 " "Info: Processing started: Wed Dec 14 11:12:41 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seg71 -c seg71 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg71 -c seg71" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg71.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file seg71.v" { { "Info" "ISGN_ENTITY_NAME" "1 seg71 " "Info: Found entity 1: seg71" {  } { { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seg71 " "Info: Elaborating entity \"seg71\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 seg71.v(22) " "Warning: Verilog HDL assignment warning at seg71.v(22): truncated value with size 32 to match size of target (16)" {  } { { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 seg71.v(26) " "Warning: Verilog HDL assignment warning at seg71.v(26): truncated value with size 32 to match size of target (16)" {  } { { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 26 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_scan\[0\]~0 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_scan\[0\]~0\"" {  } { { "seg71.v" "cnt_scan\[0\]~0" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "seg71.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/7段数码管/seg71/seg71.v" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "50 " "Info: Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "32 " "Info: Implemented 32 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 11:12:42 2005 " "Info: Processing ended: Wed Dec 14 11:12:42 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}