key1.map.qmsg

几个常用的接口实验的程序代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 12:07:15 2005 " "Info: Processing started: Wed Dec 14 12:07:15 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off key1 -c key1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key1 -c key1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key1.v" { { "Info" "ISGN_ENTITY_NAME" "1 key1 " "Info: Found entity 1: key1" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "key1 " "Info: Elaborating entity \"key1\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 key1.v(18) " "Warning: Verilog HDL assignment warning at key1.v(18): truncated value with size 32 to match size of target (8)" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 key1.v(24) " "Warning: Verilog HDL assignment warning at key1.v(24): truncated value with size 32 to match size of target (16)" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 key1.v(27) " "Warning: Verilog HDL assignment warning at key1.v(27): truncated value with size 32 to match size of target (16)" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "key1.v(44) " "Warning: (10270) Verilog HDL statement warning at key1.v(44): incomplete Case Statement has no default case item" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "key1.v(59) " "Warning: (10270) Verilog HDL statement warning at key1.v(59): incomplete Case Statement has no default case item" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "key1.v(74) " "Warning: (10270) Verilog HDL statement warning at key1.v(74): incomplete Case Statement has no default case item" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "key1.v(89) " "Warning: (10270) Verilog HDL statement warning at key1.v(89): incomplete Case Statement has no default case item" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 89 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_scan\[0\]~0 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_scan\[0\]~0\"" {  } { { "key1.v" "cnt_scan\[0\]~0" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|key1\|scan_key 16 0 " "Info: State machine \"\|key1\|scan_key\" contains 16 states and 0 state bits" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|key1\|scan_key " "Info: Selected Auto state machine encoding method for state machine \"\|key1\|scan_key\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|key1\|scan_key " "Info: Encoding result for state machine \"\|key1\|scan_key\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key~53 " "Info: Encoded state bit \"scan_key~53\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key~52 " "Info: Encoded state bit \"scan_key~52\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key~51 " "Info: Encoded state bit \"scan_key~51\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key~50 " "Info: Encoded state bit \"scan_key~50\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0000 0000 " "Info: State \"\|key1\|scan_key.0000\" uses code string \"0000\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1110 0010 " "Info: State \"\|key1\|scan_key.1110\" uses code string \"0010\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1101 0011 " "Info: State \"\|key1\|scan_key.1101\" uses code string \"0011\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1100 0110 " "Info: State \"\|key1\|scan_key.1100\" uses code string \"0110\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1011 0100 " "Info: State \"\|key1\|scan_key.1011\" uses code string \"0100\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1010 0101 " "Info: State \"\|key1\|scan_key.1010\" uses code string \"0101\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1001 0111 " "Info: State \"\|key1\|scan_key.1001\" uses code string \"0111\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1000 1000 " "Info: State \"\|key1\|scan_key.1000\" uses code string \"1000\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0111 1001 " "Info: State \"\|key1\|scan_key.0111\" uses code string \"1001\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0110 1010 " "Info: State \"\|key1\|scan_key.0110\" uses code string \"1010\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0101 1011 " "Info: State \"\|key1\|scan_key.0101\" uses code string \"1011\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0100 1100 " "Info: State \"\|key1\|scan_key.0100\" uses code string \"1100\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0011 1101 " "Info: State \"\|key1\|scan_key.0011\" uses code string \"1101\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0010 1110 " "Info: State \"\|key1\|scan_key.0010\" uses code string \"1110\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0001 1111 " "Info: State \"\|key1\|scan_key.0001\" uses code string \"1111\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1111 0001 " "Info: State \"\|key1\|scan_key.1111\" uses code string \"0001\"" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0}  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 9 -1 0 } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 9 -1 0 } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 9 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] GND " "Warning: Pin \"en\[1\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] GND " "Warning: Pin \"en\[2\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] GND " "Warning: Pin \"en\[3\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] GND " "Warning: Pin \"en\[4\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] GND " "Warning: Pin \"en\[5\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] GND " "Warning: Pin \"en\[6\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] GND " "Warning: Pin \"en\[7\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "79 " "Info: Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "52 " "Info: Implemented 52 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 12:07:24 2005 " "Info: Processing ended: Wed Dec 14 12:07:24 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}