key1.tan.qmsg

几个常用的接口实验的程序代码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[1\] scan_key~50 17.000 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[1\]\" through register \"scan_key~50\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns scan_key~50 2 REG LC84 40 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC84; Fanout = 40; REG Node = 'scan_key~50'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "0.000 ns" { clk scan_key~50 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~50 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~50 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_key~50 1 REG LC84 40 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC84; Fanout = 40; REG Node = 'scan_key~50'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { scan_key~50 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns reduce_or~351 2 COMB LC99 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC99; Fanout = 1; COMB Node = 'reduce_or~351'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "9.000 ns" { scan_key~50 reduce_or~351 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns dataout\[1\] 3 PIN PIN_64 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'dataout\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "4.000 ns" { reduce_or~351 dataout[1] } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "13.000 ns" { scan_key~50 reduce_or~351 dataout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { scan_key~50 reduce_or~351 dataout[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~50 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~50 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "13.000 ns" { scan_key~50 reduce_or~351 dataout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { scan_key~50 reduce_or~351 dataout[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "scan_key~50 column\[3\] clk -3.000 ns register " "Info: th for register \"scan_key~50\" (data pin = \"column\[3\]\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns scan_key~50 2 REG LC84 40 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC84; Fanout = 40; REG Node = 'scan_key~50'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "0.000 ns" { clk scan_key~50 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~50 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~50 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns column\[3\] 1 PIN PIN_39 37 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 37; PIN Node = 'column\[3\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { column[3] } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns scan_key~50 2 REG LC84 40 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC84; Fanout = 40; REG Node = 'scan_key~50'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "8.000 ns" { column[3] scan_key~50 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "10.000 ns" { column[3] scan_key~50 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { column[3] column[3]~out scan_key~50 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~50 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~50 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "10.000 ns" { column[3] scan_key~50 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { column[3] column[3]~out scan_key~50 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 12:07:32 2005 " "Info: Processing ended: Wed Dec 14 12:07:32 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}