📄 key1.tan.qmsg
字号:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register row\[1\]~reg0 register scan_key~52 62.5 MHz 16.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 62.5 MHz between source register \"row\[1\]~reg0\" and destination register \"scan_key~52\" (period= 16.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest register register " "Info: + Longest register to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns row\[1\]~reg0 1 REG LC35 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 42; REG Node = 'row\[1\]~reg0'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { row[1]~reg0 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns scan_key~16696 2 COMB LC53 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC53; Fanout = 1; COMB Node = 'scan_key~16696'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "8.000 ns" { row[1]~reg0 scan_key~16696 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns scan_key~16701 3 COMB LC54 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC54; Fanout = 1; COMB Node = 'scan_key~16701'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "1.000 ns" { scan_key~16696 scan_key~16701 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.000 ns scan_key~16707 4 COMB LC55 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC55; Fanout = 1; COMB Node = 'scan_key~16707'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "1.000 ns" { scan_key~16701 scan_key~16707 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns scan_key~52 5 REG LC56 39 " "Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC56; Fanout = 39; REG Node = 'scan_key~52'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "1.000 ns" { scan_key~16707 scan_key~52 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 81.82 % " "Info: Total cell delay = 9.000 ns ( 81.82 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 18.18 % " "Info: Total interconnect delay = 2.000 ns ( 18.18 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "11.000 ns" { row[1]~reg0 scan_key~16696 scan_key~16701 scan_key~16707 scan_key~52 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { row[1]~reg0 scan_key~16696 scan_key~16701 scan_key~16707 scan_key~52 } { 0.000ns 2.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns scan_key~52 2 REG LC56 39 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC56; Fanout = 39; REG Node = 'scan_key~52'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "0.000 ns" { clk scan_key~52 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~52 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~52 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns row\[1\]~reg0 2 REG LC35 42 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC35; Fanout = 42; REG Node = 'row\[1\]~reg0'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "0.000 ns" { clk row[1]~reg0 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk row[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out row[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~52 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~52 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk row[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out row[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "11.000 ns" { row[1]~reg0 scan_key~16696 scan_key~16701 scan_key~16707 scan_key~52 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { row[1]~reg0 scan_key~16696 scan_key~16701 scan_key~16707 scan_key~52 } { 0.000ns 2.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns 1.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~52 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~52 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk row[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out row[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "scan_key~51 column\[1\] clk 19.000 ns register " "Info: tsu for register \"scan_key~51\" (data pin = \"column\[1\]\", clock pin = \"clk\") is 19.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.000 ns + Longest pin register " "Info: + Longest pin to register delay is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns column\[1\] 1 PIN PIN_36 39 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_36; Fanout = 39; PIN Node = 'column\[1\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { column[1] } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns scan_key~16662 2 COMB SEXP49 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'scan_key~16662'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "10.000 ns" { column[1] scan_key~16662 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns scan_key~51 3 REG LC60 26 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC60; Fanout = 26; REG Node = 'scan_key~51'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "6.000 ns" { scan_key~16662 scan_key~51 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 88.89 % " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 11.11 % " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "18.000 ns" { column[1] scan_key~16662 scan_key~51 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "18.000 ns" { column[1] column[1]~out scan_key~16662 scan_key~51 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns scan_key~51 2 REG LC60 26 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC60; Fanout = 26; REG Node = 'scan_key~51'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "0.000 ns" { clk scan_key~51 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~51 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~51 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "18.000 ns" { column[1] scan_key~16662 scan_key~51 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "18.000 ns" { column[1] column[1]~out scan_key~16662 scan_key~51 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/矩阵键盘/key1/" "" "3.000 ns" { clk scan_key~51 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out scan_key~51 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0}
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