config_controller.tdf

IIR、FIR、FFT各模块程序设计例程

----------------------------------------------------------------
-- config_controller.tdf            note: dclk = 3.125MHz
--
--   For Nios/Cyclone Standard (1C20) Development board. 
--
----------------------------------------------------------------
-- This file contains a design (config_controller) which fits in a EPM7128AE
-- device.  It connects to one 8MByte AMD AM29LV065D FLASH memory
-- device.
--
-- This particular design is set up for a 50MHz input clock frequency.  You 
-- can set it up for any input clock frequency you want by changing the
-- "dclk_divider" preload value.
--
-- Upon reset, flash_config will parallel read, then serial-program the 
-- Cyclone device using configuration data stored in the attached flash
-- memory.  The config_controller is a sequencer and address-generator
-- which causes the right data, at the right time, to appear
-- on the Cyclone devices' programming pins.  When flash_config
-- is done programming the Cyclone chip, it "removes itself from
-- the circuit" by tri-stating  all its outputs 
-- (except where specifically noted).
--
-- The flash may contain two separate Cyclone configurations.  For the purpose
-- of this discussion, we will call one configuration "User," and the
-- other configuration "Safe."  The config_controller will
-- -first- attempt to load the Cyclone chip with the User configuration.  If 
-- this fails, it will then attempt to load the Cyclone chip with the Safe
-- configuration.  The idea is:  The User configuration is some design
-- under-development, and the "Safe" configuration is the
-- known-to-work backup in case that doesn't work.  In fact, Altera
-- ships the development board with a factory-programmed Safe configuration
-- that users SHOULD NEVER ERASE OR REPLACE.
--
-- This design can be forced to load the Safe configuration first, 
-- (without first attempting to load the User configuration), by holding
-- the "safe_config" input low (0V).
--
-- The pins on the config_controller design are connected 
-- according to the comments next to each I/O declaration in the 
-- SUBDESIGN section, below.  In addition to those connections, 
-- the FLASH data bits 0..7 must also be connected to the EPM7128AE
-- devices' DATA0 .. DATA7 programming pins. 
--
--
-- The Cyclone device should be wired-up for Passive Serial mode
-- (PS) mode.  Here's how to drive the mode-select pins:
--
--              MSEL0:   Low  (0) |Active Serial mode
--              MSEL1:   Low  (0) | 
--              
--              MSEL0:   High (1) |Passive Serial mode
--              MSEL1:   Low  (0) | 
--
-- Q: What kind of data should the FLASH memory contain?
--
-- A: The FLASH needs to contain a valid Cyclone configuration.
--    Happily, One of Quartus' several output-formats is 
--    "hexout" (Intel Hexadecimal file format, aka IHEX).
--    The hexout-files produced by Quartus directly
--    specifies the contents of the FLASH memory.  Most
--    device-programmers and embedded CPU boot monitors 
--    understand IHEX format files.  The Nios boot-monitor,
--    in particular, can download Quartus' hexout-output directly
--    into AMD flash where it can be used as configuration data
--    by this design (flash_config).  The contents of this IHEX
--    file should be loaded into the FLASH starting at OFFSET
--    0x600000.  You can alter the start-address by changing
--    how the upper bits of the FLASH address are set.
--
-- Q: I want to program a different part (not Cyclone EP1C20)!  What do I do?
-- 
-- A: Indeed, several assumptions about the particular device and 
--    flash-memory 
--
--
-- FEATURE:  FPGA Self-Configuration.
--
--      Sophisticated FPGA designs (e.g. CPU systems)
--      might wish to reconfigure themselves.  This design 
--      supports that functionality by providing the "config_request" 
--      input.  If you drive this pin low (0V), it will restart
--      the configure-from-flash sequence.  If you use this feature,
--      be sure the correspondig FPGA pin has a pull-up resistor so
--      that an unconfigured FPGA (or an FPGA design with no knowledge
--      of this pin) isn't constantly reconfiguring itself.
--
-- BONUS FEATURE: Reset distribution
--
--   The config_controller design has a second, almost-independent
--   function built-in: Board-level reset-signal distribution. Various 
--   on-board devices take different reset logic-senses, so it is 
--   natural to derive individual device-resets from the master
--   (power-on) reset using the MAX device.  As a side-effect, this 
--   also lets the FPGA force a board-level reset when it asserts its
--   config_request output.
-- 
--
----------------------------------------------------------------

TITLE   "config_controller";

INCLUDE "dclk_divider";
INCLUDE "address_counter";
-- JMC Changes
INCLUDE "cf_rst_cnt";
INCLUDE "cf_counter";
-- end
INCLUDE "data_bit_counter";
INCLUDE "shift_register";
INCLUDE "reset_counter";

SUBDESIGN config_controller
(
 cpld_CLKOSC        : INPUT;    -- 50MHz oscillator clock frequency 
 RESET_n            : INPUT;    -- from the reset chip
 STATUS_n           : INPUT;    -- from the Cyclone
 config_request_n   : INPUT;    -- FPGA can Request SELF-CONFIG
 safe_config_n      : INPUT;    -- Safe Config if button pressed 
                                -- or User Config fails to load properly
                                
 flash_A22          : OUTPUT;   -- A22/A21 Driven to 1.  Uses top 1/4
 flash_A21          : OUTPUT;   --   of flash for config images
 flash_A20          : OUTPUT;   -- This is the user/safe image selector
 A[19..0]           : OUTPUT;   -- 2^20 is big enough for 1S10 image.
 D[7..0]            : INPUT;    -- output serialized flash data to pld_DATA0
 pld_DATA0          : BIDIR;    -- Serial data to the Cyclone from ASMI (active)
                                --                         or from Max  (serial)

 CONFIG_n           : OUTPUT;   -- from MAX to the Cyclone
 CONFIG_DONE        : INPUT;    -- from Cyclone to Max when done        
 DCLK               : BIDIR;    -- data clock from Max to Cyclone in serial, 
                                --            from Cyclone to ASMI in active.
-- INIT_DONE          : INPUT; -- indicates user ready Cyclone

 flash_CS_n         : OUTPUT;   -- flash control signals
 flash_OE_n         : OUTPUT;
 flash_RW_n         : OUTPUT;
-- flash_RY_BY_n      : INPUT;    -- useful when waiting for flash

                    
 flash_reset_n      : OUTPUT;  -- MAX device used to distribute reset.
 enet_reset         : OUTPUT;  
 proto1_reset_n     : OUTPUT;
 proto2_reset_n     : OUTPUT; 

 pld_MSEL0          : OUTPUT;  -- Configuration pins. Tell Cyclone chip 
 pld_MSEL1          : OUTPUT;  --    what configuration mode to use. 
-- pld_CS_n           : INPUT;   -- chipselect for ASMI device
-- pld_ASDO           : BIDIR;   -- Active Serial Data Out from Cyclone to ASMI

 loading_led        : OUTPUT;  -- indicators for each LED
 error_led          : OUTPUT;
 user_led           : OUTPUT;
 safe_led           : OUTPUT;

 enet_VLBUS_n       : OUTPUT; -- added to reset ethernet chip on the 1C20 Dev kit

-- user_PB0           : INPUT; 
-- user_PB1           : INPUT;  
-- user_PB2           : INPUT;
-- user_PB3           : INPUT;


-- Input declarations for DEBUG purposes (commented out before programming).
-- Quartus simulator isn't friendly with nodes (no respect), so these temporary
-- outputs can be used to produce simulation signals that cannot be synthesized
-- out by Quartus.
--
-- DCLKQ3_STATE         : OUTPUT; -- dclk q[3] AND state_counting (clkosc divide by 16)
-- DCLKCOUT             : OUTPUT; -- dclk_divider.cout 
-- DBCNTCOUT            : OUTPUT; -- data_bit_counter.cout
-- STATE_CNTG           : OUTPUT; -- state_counting
-- DRIVE_OUT            : OUTPUT; -- drive_outputs
--



)

VARIABLE

  -- instantiate these counters and a shift register
  The_Dclk_Divider           : dclk_divider; 
  The_Address_Counter        : address_counter;
-- JMC Changes
  The_CF_RST_Counter         : cf_rst_cnt;
  The_CF_Counter             : cf_counter;
-- end  
  The_Data_Bit_Counter       : data_bit_counter;
  The_Shift_Register         : shift_register;
  The_Reset_Counter          : reset_counter;
 
  obuf_flash_A22             : TRI;    -- output buffers for outgoing signals
  obuf_flash_A21             : TRI;
  obuf_flash_A20             : TRI;
  obuf_A[19..0]              : TRI;

  obuf_flash_CS_n            : TRI; 
  obuf_flash_OE_n            : TRI; 
  obuf_flash_RW_n            : TRI; 
  obuf_DCLK                  : TRI;
  obuf_pld_DATA0             : TRI;

  obuf_CONFIG_n_oe	     : TRI;  -- SPR 128193
         
  CONFIG_n_reg               : DFFE;  -- registered logic signals
  State_Waiting_For_STATUS_n : DFFE;
  State_Counting             : DFFE;
  State_Done                 : DFFE;
  State_Error                : DFFE;
  State_JTAG_Config          : DFFE;        

  try_asmi_config            : DFF;  

  eek_an_error               : DFF;
  try_user_config            : DFF;
  counter_wrapped            : DFF;
  d1_safe_config             : DFFE;
  d2_safe_config             : DFFE;
  d1_reset_source            : DFFE;
  d2_reset_source            : DFFE;
  cause_was_safe_config      : DFF;
  sync_config_request        : DFF;        
  Reset_Pulse                : DFF;
-- JMC Changes
  cf_Reset_Pulse             : DFF;
-- end

  -- Logic Nodes  
  --   (Hint: If you ever want to see "NODEs"  while simulating, you are
  --   advised to add temporary output pins that they  must be assigned to.
  --   Only then will Quartus simulator demonstrate proper simulation.)  
  restart_sequence           : NODE; 
  dclkq3_stcntg              : NODE; 
  dclk_en                    : NODE; 
  drive_outputs              : NODE; 
  safe_config_rising_edge    : NODE; 
  reset_source_rising_edge   : NODE; 
  reset_source               : NODE; 
  byte_count_en              : NODE;
  load                       : NODE; 
  DATA0                      : NODE;
  user_led_blinking          : NODE;

BEGIN

  ----------------
  -- The_Shift_Register 
  --
  -- When Data_Bit_Counter = [000], 1 bit shiftout gets data from D[7..0]
  -- shifts out through pld_DATA0 to the Cyclone one bit per Data_Bit_Counter
  -- cycle.
 
        -- High (1): load operation
        -- Low  (0): shift operation
 load   = The_Data_Bit_Counter.cout; -- all three low loads shift register
-- load     = !The_Data_Bit_Counter.q[2]  -- all three low loads shift register
--      & !The_Data_Bit_Counter.q[1]        -- High (1): load operation
--      & !The_Data_Bit_Counter.q[0];       -- Low (0): shift operation
        
  The_Shift_Register.load = load; -- let's make a shorter name to our useful
                                  -- load pin

  The_Shift_Register.data[6..0] = D[7..1];  -- scoot the rest into the shift
                                            -- register (to shiftout)