config_controller.psf

IIR、FIR、FFT各模块程序设计例程

DEFAULT_DESIGN_ASSISTANT_SETTINGS
{
	HCPY_ALOAD_SIGNALS = OFF;
	HCPY_VREF_PINS = OFF;
	HCPY_CAT = OFF;
	HCPY_ILLEGAL_HC_DEV_PKG = OFF;
	ACLK_RULE_IMSZER_ADOMAIN = OFF;
	ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
	ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
	ACLK_CAT = OFF;
	SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
	SIGNALRACE_CAT = OFF;
	NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
	NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
	NONSYNCHSTRUCT_RULE_DLATCH = OFF;
	NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
	NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
	NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
	NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
	NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
	NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
	NONSYNCHSTRUCT_CAT = OFF;
	TIMING_RULE_COIN_CLKEDGE = OFF;
	TIMING_RULE_SHIFT_REG = OFF;
	TIMING_RULE_HIGH_FANOUTS = OFF;
	TIMING_CAT = OFF;
	RESET_RULE_ALL = OFF;
	RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
	RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
	RESET_RULE_REG_ASNYCH = OFF;
	RESET_RULE_COMB_ASYNCH_RESET = OFF;
	RESET_RULE_IMSYNCH_EXRESET = OFF;
	RESET_RULE_UNSYNCH_EXRESET = OFF;
	RESET_RULE_INPINS_RESETNET = OFF;
	RESET_CAT = OFF;
	CLK_RULE_ALL = OFF;
	CLK_RULE_MIX_EDGES = OFF;
	CLK_RULE_CLKNET_CLKSPINES = OFF;
	CLK_RULE_INPINS_CLKNET = OFF;
	CLK_RULE_GATING_SCHEME = OFF;
	CLK_RULE_INV_CLOCK = OFF;
	CLK_RULE_COMB_CLOCK = OFF;
	CLK_CAT = OFF;
	HCPY_EXCEED_USER_IO_USAGE = OFF;
	HCPY_EXCEED_RAM_USAGE = OFF;
}
SYNTHESIS_FITTING_SETTINGS
{
	REMOVE_DUPLICATE_LOGIC = OFF;
	AUTO_TURBO_BIT = ON;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_PARALLEL_EXPANDERS = ON;
	MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
	AUTO_LCELL_INSERTION = ON;
	ALLOW_XOR_GATE_USAGE = ON;
	MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
	AUTO_GLOBAL_REGISTER_CONTROLS = ON;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_CLOCK = ON;
	LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
	MAX7000_IGNORE_SOFT_BUFFERS = OFF;
	IGNORE_LCELL_BUFFERS = OFF;
	IGNORE_ROW_GLOBAL_BUFFERS = OFF;
	IGNORE_GLOBAL_BUFFERS = OFF;
	IGNORE_CASCADE_BUFFERS = OFF;
	IGNORE_CARRY_BUFFERS = OFF;
	REMOVE_DUPLICATE_REGISTERS = OFF;
	REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
	ALLOW_POWER_UP_DONT_CARE = ON;
	NOT_GATE_PUSH_BACK = ON;
	SLOW_SLEW_RATE = OFF;
	STATE_MACHINE_PROCESSING = AUTO;
}
DEFAULT_HARDCOPY_SETTINGS
{
	HCPY_GEN_FILES_DURING_COMPILATION = OFF;
	HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 ns";
	HARDCOPY_MINIMUM_REQUIRED_TPD = "0.0 ns";
	HARDCOPY_MINIMUM_REQUIRED_TCO = "0.0 ns";
}
DEFAULT_TIMING_REQUIREMENTS
{
	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
	RUN_ALL_TIMING_ANALYSES = OFF;
	IGNORE_CLOCK_SETTINGS = ON;
	DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_READ_DURING_WRITE_PATHS = ON;
	CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = OFF;
	NUMBER_OF_PATHS_TO_REPORT = 200;
	NUMBER_OF_DESTINATION_TO_REPORT = 10;
	NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
	MAX_SCC_SIZE = 50;
}
HDL_SETTINGS
{
	VERILOG_INPUT_VERSION = VERILOG_2001;
	VHDL_INPUT_VERSION = VHDL93;
	VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
}
PROJECT_INFO(config_controller)
{
	ORIGINAL_QUARTUS_VERSION = 2.2;
	LAST_QUARTUS_VERSION = 2.2;
	SHOW_REGISTRATION_MESSAGE = ON;
}