addrlogic.tan.qmsg

来自「基于matlab的gmsk信号的调制」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "7474:18\|9 data clock -0.800 ns register " "Info: th for register \"7474:18\|9\" (data pin = \"data\", clock pin = \"clock\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.300 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { clock } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 608 48 216 624 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns 7474:18\|9 2 REG LC11 1 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18\|9'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.100 ns" { clock 7474:18|9 } "NODE_NAME" } "" } } { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 7474:18|9 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns data 1 PIN PIN_21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 2; PIN Node = 'data'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { data } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 736 0 168 752 "data" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns 7474:18\|9 2 REG LC11 1 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18\|9'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.600 ns" { data 7474:18|9 } "NODE_NAME" } "" } } { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 73.68 % ) " "Info: Total cell delay = 2.800 ns ( 73.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 26.32 % ) " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.800 ns" { data 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.800 ns" { data data~out 7474:18|9 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 7474:18|9 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.800 ns" { data 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.800 ns" { data data~out 7474:18|9 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 04 23:00:57 2008 " "Info: Processing ended: Wed Jun 04 23:00:57 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}