addrlogic.tan.qmsg

来自「基于matlab的gmsk信号的调制」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 608 48 216 624 "clock" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register 7474:1\|9 register 74169:4\|15 87.72 MHz 11.4 ns Internal " "Info: Clock \"clock\" has Internal fmax of 87.72 MHz between source register \"7474:1\|9\" and destination register \"74169:4\|15\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7474:1\|9 1 REG LC4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = '7474:1\|9'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { 7474:1|9 } "NODE_NAME" } "" } } { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns 74169:4\|15 2 REG LC1 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4\|15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.600 ns" { 7474:1|9 74169:4|15 } "NODE_NAME" } "" } } { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { 184 1264 1328 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 72.22 % ) " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 27.78 % ) " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.600 ns" { 7474:1|9 74169:4|15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { 7474:1|9 74169:4|15 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { clock } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 608 48 216 624 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns 74169:4\|15 2 REG LC1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4\|15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.100 ns" { clock 74169:4|15 } "NODE_NAME" } "" } } { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { 184 1264 1328 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 74169:4|15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 74169:4|15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { clock } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 608 48 216 624 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns 7474:1\|9 2 REG LC4 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC4; Fanout = 2; REG Node = '7474:1\|9'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.100 ns" { clock 7474:1|9 } "NODE_NAME" } "" } } { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 7474:1|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 7474:1|9 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 74169:4|15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 74169:4|15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 7474:1|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 7474:1|9 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { 184 1264 1328 264 "15" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } } { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { 184 1264 1328 264 "15" "" } } } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.600 ns" { 7474:1|9 74169:4|15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { 7474:1|9 74169:4|15 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 74169:4|15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 74169:4|15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 7474:1|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 7474:1|9 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "7474:18\|9 data clock 3.300 ns register " "Info: tsu for register \"7474:18\|9\" (data pin = \"data\", clock pin = \"clock\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest pin register " "Info: + Longest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns data 1 PIN PIN_21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 2; PIN Node = 'data'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { data } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 736 0 168 752 "data" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns 7474:18\|9 2 REG LC11 1 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18\|9'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.600 ns" { data 7474:18|9 } "NODE_NAME" } "" } } { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 73.68 % ) " "Info: Total cell delay = 2.800 ns ( 73.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 26.32 % ) " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.800 ns" { data 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.800 ns" { data data~out 7474:18|9 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { clock } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 608 48 216 624 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns 7474:18\|9 2 REG LC11 1 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18\|9'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.100 ns" { clock 7474:18|9 } "NODE_NAME" } "" } } { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { 64 256 320 144 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 7474:18|9 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "3.800 ns" { data 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.800 ns" { data data~out 7474:18|9 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 7474:18|9 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 7474:18|9 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock A7 74169:4\|15 2.800 ns register " "Info: tco from clock \"clock\" to destination pin \"A7\" through register \"74169:4\|15\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { clock } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 608 48 216 624 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns 74169:4\|15 2 REG LC1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4\|15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.100 ns" { clock 74169:4|15 } "NODE_NAME" } "" } } { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { 184 1264 1328 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 74169:4|15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 74169:4|15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { 184 1264 1328 264 "15" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74169:4\|15 1 REG LC1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4\|15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "" { 74169:4|15 } "NODE_NAME" } "" } } { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { 184 1264 1328 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns A7 2 PIN PIN_4 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'A7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.200 ns" { 74169:4|15 A7 } "NODE_NAME" } "" } } { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 184 672 848 200 "A7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns ( 100.00 % ) " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.200 ns" { 74169:4|15 A7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.200 ns" { 74169:4|15 A7 } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "1.300 ns" { clock 74169:4|15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out 74169:4|15 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "addrlogic" "UNKNOWN" "V1" "D:/GMSK课设/别人的GMSK/报告2/VHDL/db/addrlogic.quartus_db" { Floorplan "D:/GMSK课设/别人的GMSK/报告2/VHDL/" "" "0.200 ns" { 74169:4|15 A7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.200 ns" { 74169:4|15 A7 } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}