dianzhen.tan.qmsg

实现一个10秒倒计时电路

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 10 -1 0 } } { "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "statebutton " "Info: Assuming node statebutton is an undefined clock" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 10 -1 0 } } { "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "statebutton" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk4~reg0 " "Info: Detected ripple clock clk4~reg0 as buffer" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } } { "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk4~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clk2~reg0 " "Info: Detected ripple clock clk2~reg0 as buffer" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 59 -1 0 } } { "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk2~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clk1~reg0 " "Info: Detected ripple clock clk1~reg0 as buffer" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 39 -1 0 } } { "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/tddownload/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk1~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register qtemp4\[4\] register qtemp4\[0\] 141.96 MHz 7.044 ns Internal " "Info: Clock clk has Internal fmax of 141.96 MHz between source register qtemp4\[4\] and destination register qtemp4\[0\] (period= 7.044 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.688 ns + Longest register register " "Info: + Longest register to register delay is 6.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qtemp4\[4\] 1 REG LC_X2_Y4_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y4_N4; Fanout = 3; REG Node = 'qtemp4\[4\]'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "" { qtemp4[4] } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.380 ns) + CELL(0.472 ns) 2.852 ns reduce_nor~393 2 COMB LC_X3_Y3_N7 1 " "Info: 2: + IC(2.380 ns) + CELL(0.472 ns) = 2.852 ns; Loc. = LC_X3_Y3_N7; Fanout = 1; COMB Node = 'reduce_nor~393'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.852 ns" { qtemp4[4] reduce_nor~393 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.195 ns) + CELL(0.128 ns) 3.175 ns reduce_nor~395 3 COMB LC_X3_Y3_N8 1 " "Info: 3: + IC(0.195 ns) + CELL(0.128 ns) = 3.175 ns; Loc. = LC_X3_Y3_N8; Fanout = 1; COMB Node = 'reduce_nor~395'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "0.323 ns" { reduce_nor~393 reduce_nor~395 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.583 ns) 4.475 ns reduce_nor~3 4 COMB LC_X4_Y3_N0 13 " "Info: 4: + IC(0.717 ns) + CELL(0.583 ns) = 4.475 ns; Loc. = LC_X4_Y3_N0; Fanout = 13; COMB Node = 'reduce_nor~3'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.300 ns" { reduce_nor~395 reduce_nor~3 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.536 ns) + CELL(0.677 ns) 6.688 ns qtemp4\[0\] 5 REG LC_X3_Y3_N3 4 " "Info: 5: + IC(1.536 ns) + CELL(0.677 ns) = 6.688 ns; Loc. = LC_X3_Y3_N3; Fanout = 4; REG Node = 'qtemp4\[0\]'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.213 ns" { reduce_nor~3 qtemp4[0] } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.860 ns 27.81 % " "Info: Total cell delay = 1.860 ns ( 27.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.828 ns 72.19 % " "Info: Total interconnect delay = 4.828 ns ( 72.19 % )" {  } {  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "6.688 ns" { qtemp4[4] reduce_nor~393 reduce_nor~395 reduce_nor~3 qtemp4[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.174 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_14 64 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 64; CLK Node = 'clk'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.586 ns) 2.174 ns qtemp4\[0\] 2 REG LC_X3_Y3_N3 4 " "Info: 2: + IC(0.861 ns) + CELL(0.586 ns) = 2.174 ns; Loc. = LC_X3_Y3_N3; Fanout = 4; REG Node = 'qtemp4\[0\]'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.447 ns" { clk qtemp4[0] } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.313 ns 60.40 % " "Info: Total cell delay = 1.313 ns ( 60.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.861 ns 39.60 % " "Info: Total interconnect delay = 0.861 ns ( 39.60 % )" {  } {  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.174 ns" { clk qtemp4[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.174 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_14 64 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 64; CLK Node = 'clk'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.586 ns) 2.174 ns qtemp4\[4\] 2 REG LC_X2_Y4_N4 3 " "Info: 2: + IC(0.861 ns) + CELL(0.586 ns) = 2.174 ns; Loc. = LC_X2_Y4_N4; Fanout = 3; REG Node = 'qtemp4\[4\]'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.447 ns" { clk qtemp4[4] } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.313 ns 60.40 % " "Info: Total cell delay = 1.313 ns ( 60.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.861 ns 39.60 % " "Info: Total interconnect delay = 0.861 ns ( 39.60 % )" {  } {  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.174 ns" { clk qtemp4[4] } "NODE_NAME" } } }  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.174 ns" { clk qtemp4[0] } "NODE_NAME" } } } { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.174 ns" { clk qtemp4[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.243 ns + " "Info: + Micro clock to output delay of source is 0.243 ns" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.113 ns + " "Info: + Micro setup delay of destination is 0.113 ns" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } }  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "6.688 ns" { qtemp4[4] reduce_nor~393 reduce_nor~395 reduce_nor~3 qtemp4[0] } "NODE_NAME" } } } { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.174 ns" { clk qtemp4[0] } "NODE_NAME" } } } { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.174 ns" { clk qtemp4[4] } "NODE_NAME" } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "statebutton " "Info: No valid register-to-register paths exist for clock statebutton" {  } {  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 7 " "Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock clk with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "press\[3\]~reg0 q1\[2\]~reg0 clk 989 ps " "Info: Found hold time violation between source  pin or register press\[3\]~reg0 and destination pin or register q1\[2\]~reg0 for clock clk (Hold time is 989 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.002 ns + Largest " "Info: + Largest clock skew is 3.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.824 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 6.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_14 64 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 64; CLK Node = 'clk'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.829 ns) 2.417 ns clk1~reg0 2 REG LC_X2_Y3_N8 30 " "Info: 2: + IC(0.861 ns) + CELL(0.829 ns) = 2.417 ns; Loc. = LC_X2_Y3_N8; Fanout = 30; REG Node = 'clk1~reg0'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.690 ns" { clk clk1~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.272 ns) + CELL(0.829 ns) 4.518 ns clk2~reg0 3 REG LC_X2_Y1_N4 17 " "Info: 3: + IC(1.272 ns) + CELL(0.829 ns) = 4.518 ns; Loc. = LC_X2_Y1_N4; Fanout = 17; REG Node = 'clk2~reg0'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.101 ns" { clk1~reg0 clk2~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.720 ns) + CELL(0.586 ns) 6.824 ns q1\[2\]~reg0 4 REG LC_X5_Y1_N5 14 " "Info: 4: + IC(1.720 ns) + CELL(0.586 ns) = 6.824 ns; Loc. = LC_X5_Y1_N5; Fanout = 14; REG Node = 'q1\[2\]~reg0'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "2.306 ns" { clk2~reg0 q1[2]~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 127 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.971 ns 43.54 % " "Info: Total cell delay = 2.971 ns ( 43.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.853 ns 56.46 % " "Info: Total interconnect delay = 3.853 ns ( 56.46 % )" {  } {  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "6.824 ns" { clk clk1~reg0 clk2~reg0 q1[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.822 ns - Shortest register " "Info: - Shortest clock path from clock clk to source register is 3.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_14 64 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 64; CLK Node = 'clk'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.829 ns) 2.417 ns clk4~reg0 2 REG LC_X4_Y2_N4 5 " "Info: 2: + IC(0.861 ns) + CELL(0.829 ns) = 2.417 ns; Loc. = LC_X4_Y2_N4; Fanout = 5; REG Node = 'clk4~reg0'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.690 ns" { clk clk4~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 94 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.586 ns) 3.822 ns press\[3\]~reg0 3 REG LC_X5_Y2_N1 12 " "Info: 3: + IC(0.819 ns) + CELL(0.586 ns) = 3.822 ns; Loc. = LC_X5_Y2_N1; Fanout = 12; REG Node = 'press\[3\]~reg0'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.405 ns" { clk4~reg0 press[3]~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 112 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.142 ns 56.04 % " "Info: Total cell delay = 2.142 ns ( 56.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.680 ns 43.96 % " "Info: Total interconnect delay = 1.680 ns ( 43.96 % )" {  } {  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "3.822 ns" { clk clk4~reg0 press[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "6.824 ns" { clk clk1~reg0 clk2~reg0 q1[2]~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "3.822 ns" { clk clk4~reg0 press[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.243 ns - " "Info: - Micro clock to output delay of source is 0.243 ns" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 112 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.911 ns - Shortest register register " "Info: - Shortest register to register delay is 1.911 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns press\[3\]~reg0 1 REG LC_X5_Y2_N1 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N1; Fanout = 12; REG Node = 'press\[3\]~reg0'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "" { press[3]~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 112 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.380 ns) 0.380 ns Mux~2755 2 COMB LC_X5_Y2_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.380 ns) = 0.380 ns; Loc. = LC_X5_Y2_N1; Fanout = 1; COMB Node = 'Mux~2755'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "0.380 ns" { press[3]~reg0 Mux~2755 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.154 ns) + CELL(0.377 ns) 1.911 ns q1\[2\]~reg0 3 REG LC_X5_Y1_N5 14 " "Info: 3: + IC(1.154 ns) + CELL(0.377 ns) = 1.911 ns; Loc. = LC_X5_Y1_N5; Fanout = 14; REG Node = 'q1\[2\]~reg0'" {  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.531 ns" { Mux~2755 q1[2]~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 127 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.757 ns 39.61 % " "Info: Total cell delay = 0.757 ns ( 39.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns 60.39 % " "Info: Total interconnect delay = 1.154 ns ( 60.39 % )" {  } {  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.911 ns" { press[3]~reg0 Mux~2755 q1[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.141 ns + " "Info: + Micro hold delay of destination is 0.141 ns" {  } { { "E:/yaning8/ya3/db/dianzhen.vhd" "" "" { Text "E:/yaning8/ya3/db/dianzhen.vhd" 127 -1 0 } }  } 0}  } { { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "6.824 ns" { clk clk1~reg0 clk2~reg0 q1[2]~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "3.822 ns" { clk clk4~reg0 press[3]~reg0 } "NODE_NAME" } } } { "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" "" "" { Report "E:/yaning8/ya3/db/db/dianzhen_cmp.qrpt" Compiler "dianzhen" "UNKNOWN" "V1" "E:/yaning8/ya3/db/db/dianzhen.quartus_db" { Floorplan "" "" "1.911 ns" { press[3]~reg0 Mux~2755 q1[2]~reg0 } "NODE_NAME" } } }  } 0}