📄 dianzhen.fit.rpt
字号:
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 9 ;
; 11 ; 8 ;
; 12 ; 4 ;
; 13 ; 0 ;
; 14 ; 1 ;
+----------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 8.71) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 3 ;
; 8 ; 4 ;
; 9 ; 5 ;
; 10 ; 8 ;
; 11 ; 2 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 11.71) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 5 ;
; 11 ; 5 ;
; 12 ; 1 ;
; 13 ; 4 ;
; 14 ; 1 ;
; 15 ; 2 ;
; 16 ; 0 ;
; 17 ; 2 ;
; 18 ; 0 ;
; 19 ; 1 ;
+----------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Fri Dec 26 11:28:23 2008
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off dianzhen -c dianzhen
Info: Selected device EPM240T100C3 for design dianzhen
Info: Compilation Report contains advance information. Specifications for device EPM240T100C3 are subject to change. Contact Altera for information on availability. No programming file will be generated.
Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T100C3 is compatible
Info: No exact pin location assignment(s) for 40 pins of 40 total pins
Info: Pin clk1 not assigned to an exact location on the device
Info: Pin clk2 not assigned to an exact location on the device
Info: Pin clk3 not assigned to an exact location on the device
Info: Pin clk4 not assigned to an exact location on the device
Info: Pin row[7] not assigned to an exact location on the device
Info: Pin row[6] not assigned to an exact location on the device
Info: Pin row[5] not assigned to an exact location on the device
Info: Pin row[4] not assigned to an exact location on the device
Info: Pin row[3] not assigned to an exact location on the device
Info: Pin row[2] not assigned to an exact location on the device
Info: Pin row[1] not assigned to an exact location on the device
Info: Pin row[0] not assigned to an exact location on the device
Info: Pin col[7] not assigned to an exact location on the device
Info: Pin col[6] not assigned to an exact location on the device
Info: Pin col[5] not assigned to an exact location on the device
Info: Pin col[4] not assigned to an exact location on the device
Info: Pin col[3] not assigned to an exact location on the device
Info: Pin col[2] not assigned to an exact location on the device
Info: Pin col[1] not assigned to an exact location on the device
Info: Pin col[0] not assigned to an exact location on the device
Info: Pin voice not assigned to an exact location on the device
Info: Pin q1[3] not assigned to an exact location on the device
Info: Pin q1[2] not assigned to an exact location on the device
Info: Pin q1[1] not assigned to an exact location on the device
Info: Pin q1[0] not assigned to an exact location on the device
Info: Pin press[3] not assigned to an exact location on the device
Info: Pin press[2] not assigned to an exact location on the device
Info: Pin press[1] not assigned to an exact location on the device
Info: Pin press[0] not assigned to an exact location on the device
Info: Pin q[7] not assigned to an exact location on the device
Info: Pin q[6] not assigned to an exact location on the device
Info: Pin q[5] not assigned to an exact location on the device
Info: Pin q[4] not assigned to an exact location on the device
Info: Pin q[3] not assigned to an exact location on the device
Info: Pin q[2] not assigned to an exact location on the device
Info: Pin q[1] not assigned to an exact location on the device
Info: Pin q[0] not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin countbutton not assigned to an exact location on the device
Info: Pin statebutton not assigned to an exact location on the device
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal clk to use Global clock in PIN 14
Info: Automatically promoted signal statebutton to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal clk1~reg0 to use Global clock
Info: Destination clk1 may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal clk2~reg0 to use Global clock
Info: Destination clk2 may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Start DSP scan-chain inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into LUTs to improve timing and density
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 38 (unused VREF, 3.30 VCCIO, 1 input, 37 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 36 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 42 pins available
Info: Details of I/O bank after I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 36 pins available
Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 38 total pin(s) used -- 4 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 1.322 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y1; Fanout = 13; REG Node = 'q1[3]~reg0'
Info: 2: + IC(0.258 ns) + CELL(1.064 ns) = 1.322 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'q1[3]'
Info: Total cell delay = 1.064 ns ( 80.48 % )
Info: Total interconnect delay = 0.258 ns ( 19.52 % )
Info: Estimated interconnect usage is 30% of the available device resources
Info: Fitter placement operations ending: elapsed time = 1 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin col[7] has GND driving its datain port
Info: Pin col[6] has GND driving its datain port
Info: Pin col[0] has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Fri Dec 26 11:28:28 2008
Info: Elapsed time: 00:00:04
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -