packet_control.vhd

uart VHDL code : include tx,rx,parity bit control

------------------------------------------------------------------------------
-- Project 		: Main Receiver
-- Programmer	: Byungchan Son
-- Function		: 滚胶 力绢
-- Language		: VHDL
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--============================================================================
-- 涝免仿 器飘 沥狼
--============================================================================
entity packet_control is
	port(
		-- 矫胶袍 脚龋
		reset : in std_logic;
		clock : in std_logic;
		-- CPU interface
		ale : in std_logic;
		wr_n : in std_logic;
		rd_n : in std_logic;
		addr : in std_logic_vector(7 downto 0);
		data_in : in std_logic_vector(7 downto 0);
		data_out : out std_logic_vector(7 downto 0);
		com_rs232 : out std_logic_vector(1 downto 0);
		com0_enable : out std_logic_vector(1 downto 0);
		com1_enable : out std_logic_vector(1 downto 0);
		-- COM 价荐脚扁
		-- #0
		com0_baudrate : out std_logic_vector(15 downto 0);
		com0_control : out std_logic_vector(1 downto 0);
		com0_tx_data : out std_logic_vector(7 downto 0);
		com0_tx_wrreq : out std_logic;
		com0_tx_full : in std_logic;
		com0_rx_data : in std_logic_vector(7 downto 0);
		com0_rx_rdreq : out std_logic;
		com0_rx_empty : in std_logic;
		-- #1
		com1_baudrate : out std_logic_vector(15 downto 0);
		com1_control : out std_logic_vector(1 downto 0);
		com1_tx_data : out std_logic_vector(7 downto 0);
		com1_tx_wrreq : out std_logic;
		com1_tx_full : in std_logic;
		com1_rx_data : in std_logic_vector(7 downto 0);
		com1_rx_rdreq : out std_logic;
		com1_rx_empty : in std_logic;
		-- #2
		com2_baudrate : out std_logic_vector(15 downto 0);
		com2_control : out std_logic_vector(1 downto 0);
		com2_tx_data : out std_logic_vector(7 downto 0);
		com2_tx_wrreq : out std_logic;
		com2_tx_full : in std_logic;
		com2_rx_data : in std_logic_vector(7 downto 0);
		com2_rx_rdreq : out std_logic;
		com2_rx_empty : in std_logic;
		-- #3
		com3_baudrate : out std_logic_vector(15 downto 0);
		com3_control : out std_logic_vector(1 downto 0);
		com3_tx_data : out std_logic_vector(7 downto 0);
		com3_tx_wrreq : out std_logic;
		com3_tx_full : in std_logic;
		com3_rx_data : in std_logic_vector(7 downto 0);
		com3_rx_rdreq : out std_logic;
		com3_rx_empty : in std_logic;
		-- #4
		com4_baudrate : out std_logic_vector(15 downto 0);
		com4_control : out std_logic_vector(1 downto 0);
		com4_tx_data : out std_logic_vector(7 downto 0);
		com4_tx_wrreq : out std_logic;
		com4_tx_full : in std_logic;
		com4_rx_data : in std_logic_vector(7 downto 0);
		com4_rx_rdreq : out std_logic;
		com4_rx_empty : in std_logic
		);
end packet_control;
--============================================================================
-- 备炼 沥狼