video_control.vhd

infra pen controller, cmos sensor control and sdram control

------------------------------------------------------------------------------
-- Project 		: Video Capture Control
-- Programmer	: Byungchan Son
-- Function		: Video Control - 拳搁 母媚 棺 母媚 拳搁 钎矫
-- Language		: VHDL
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity video_control is
	port(
		-- system signal
		reset : in std_logic;
		clock : in std_logic;
		-- capture main
		vpo : in std_logic_vector(7 downto 0);  -- YUV 4:2:2 in stream
		vpo_filtering : in std_logic_vector(7 downto 0);
		h_sync_in : in std_logic;
		v_sync_in : in std_logic;
		-- OSD control
		mp : out std_logic_vector(7 downto 0);	-- YUV 4:2:2 out stream
		-- main control signal
		video_control_command : in std_logic_vector(2 downto 0);
			-- 000 : display camera data
			-- 001 : capture camera data
			-- 010 : display capture data
		capture_end_sta : out std_logic;
		capture_end_ack : in std_logic;
		vsync_start : out std_logic;
		hsync_start : out std_logic;
		-- command receiver
		anti_shake : in std_logic;
		filter_depth : in std_logic_vector(1 downto 0);
		video_type : in std_logic;
		-- sdram control signal
		video_data_in : in std_logic_vector(127 downto 0);
		video_data_out : out std_logic_vector(127 downto 0);
		line_address : out std_logic_vector(9 downto 0);
		pixel_address : out std_logic_vector(6 downto 0);
		write_data_req : out std_logic;
		read_data_req : out std_logic
		-- test signal
		);
end video_control;

architecture video_control_a of video_control is

type capture_display_state is(
	idle,
	detect_vsync,
	skip_pixel,
	write_data,
	detect_hsync,
	capture_end,
	horizontal_sync0,
	horizontal_sync1,
	horizontal_sync2,
	horizontal_sync3,
	horizontal_sync4
	);


-- state machine signal
signal current_state, next_state : capture_display_state;

-- data signal
signal line_count : std_logic_vector(9 downto 0);
signal sync_line_count : std_logic_vector(9 downto 0);
signal pixel_count : std_logic_vector(10 downto 0);
signal pixel_count_fil : std_logic_vector(10 downto 0);
signal sav_flag : std_logic;
signal m_mp : std_logic_vector(7 downto 0);
signal clk_hsync : std_logic;
signal clk_vsync : std_logic;
signal m_hsync : std_logic;
signal m_vsync : std_logic;
signal m1_hsync : std_logic;
signal m1_vsync : std_logic;
signal m2_hsync : std_logic;
signal video_select : std_logic;
	-- 0 : display current video signal
	-- 1 : display capture data
signal video_data : std_logic_vector(127 downto 0);
signal sync_lost : std_logic;
signal temp_sync_lost : std_logic_vector(3 downto 0);
begin
	main: process(
		reset,
		clock,
		video_select,
		current_state,
		next_state,
		video_control_command,
		m_vsync,
		v_sync_in,
		m_hsync,
		h_sync_in,
		line_count,
		pixel_count,
		capture_end_ack
		)
	begin
		if(reset = '1')then
			-- stste mschine
			next_state <= idle;
			-- internal signal
			line_count <= (others => '0');
			pixel_count <= (others => '0');
			sav_flag <= '0';
			m_mp <= (others => '0');
			clk_hsync <= '0';
			clk_vsync <= '0';
			m_hsync <= '0';
			m_vsync <= '0';
			video_select <= '0';
			write_data_req <= '0';
			read_data_req <= '0';
			video_data <= (others => '0');
			capture_end_sta <= '0';
			vsync_start <= '0';
			hsync_start <= '0';
		elsif(clock'event and clock = '1')then
			mp <= vpo;
		end if;
		current_state <= next_state;
	end process;
	-- sync detect process
	sync: process(
		reset,
		clock,
		m_vsync,
		v_sync_in,
		m_hsync,
		h_sync_in,
		sync_line_count
		)
	begin
		if(reset = '1')then
			-- stste mschine
			-- internal signal
			sync_lost <= '0';
			temp_sync_lost <= "0000";
			sync_line_count <= (others => '0');
		elsif(clock'event and clock = '1')then
			m1_vsync <= clk_vsync;
			m1_hsync <= clk_hsync;
			if(m1_vsync = '0' and clk_vsync = '1')then
				if(sync_lost = '1')then
					if(temp_sync_lost = "0011")then
						sync_line_count <= (others => '0');
						temp_sync_lost <= (others => '0');
						sync_lost <= '0';
					else
						temp_sync_lost <= temp_sync_lost + 1;
					end if;
				else
					sync_line_count <= (others => '0');
				end if;
			else
				if(m1_hsync = '0' and clk_hsync = '1')then
					if(sync_line_count < "1111111111")then
						sync_line_count <= sync_line_count + 1;
					else
						sync_lost <= '1';
					end if;
				end if;
			end if;
		end if;
	end process;
end video_control_a;