command_receiver.vhd

infra pen controller, cmos sensor control and sdram control

		dy_count,
		image_wrack
		)
	begin
		if(reset = '1')then
			-- stste mschine
			next_state <= idle;
			-- internal signal
			osd_command <= (others => '0');
			osd_data_no <= (others => '0');
			osd_px <= (others => '0');
			osd_py <= (others => '0');
			osd_dx <= (others => '0');
			osd_dy <= (others => '0');
			osd1_command <= (others => '0');
			osd1_data_no <= (others => '0');
			osd1_px <= (others => '0');
			osd1_py <= (others => '0');
			osd1_dx <= (others => '0');
			osd1_dy <= (others => '0');
			osd2_command <= (others => '0');
			osd2_data_no <= (others => '0');
			osd2_px <= (others => '0');
			osd2_py <= (others => '0');
			osd2_dx <= (others => '0');
			osd2_dy <= (others => '0');
			osd3_command <= (others => '0');
			osd3_data_no <= (others => '0');
			osd3_px <= (others => '0');
			osd3_py <= (others => '0');
			osd3_dx <= (others => '0');
			osd3_dy <= (others => '0');
			data_no <= (others => '0');
			data_code <= (others => '0');
			temp_osd_command <= (others => '0');
			temp_osd_px <= (others => '0');
			temp_osd_py <= (others => '0');
			temp_osd_dx <= (others => '0');
			temp_osd_dy <= (others => '0');
			image_data <= (others => '0');
			image_wrreq <= '0';
			byte_count <= (others => '0');
			dx_count <= (others => '0');
			dy_count <= (others => '0');
			image_address <= (others => '0');
			address_count <= (others => '0');
			delay_count <= (others => '0');
			length_address <= (others => '0');
			length_data <= (others => '0');
			length_wren <= '0';
			transparency <= (others => '0');
			transparency1 <= (others => '0');
			transparency2 <= (others => '0');
			transparency3 <= (others => '0');
			temp_transparency <= (others => '0');
		elsif(clock'event and clock = '1')then
			case current_state is
				when idle =>
					length_wren <= '0';
					if(receive_flag = '1')then
						if(receive_data = X"05")then
							next_state <= rx_code;
						end if;
					end if;
				when rx_code =>
					if(receive_flag = '1')then
						data_code <= receive_data;
						next_state <= rx_data_no;
					end if;
				when rx_data_no =>
					if(receive_flag = '1')then
						data_no <= receive_data;
						if(data_code = X"00")then
							next_state <= rx_data_dx_h;
						else
							next_state <= rx_data_sx_h;
						end if;
					end if;
				when rx_data_sx_h =>
					if(receive_flag = '1')then
						temp_osd_px(15 downto 8) <= receive_data;
						next_state <= rx_data_sx_l;
					end if;
				when rx_data_sx_l =>
					if(receive_flag = '1')then
						temp_osd_px(7 downto 0) <= receive_data;
						next_state <= rx_data_sy_h;
					end if;
				when rx_data_sy_h =>
					if(receive_flag = '1')then
						temp_osd_py(15 downto 8) <= receive_data;
						next_state <= rx_data_sy_l;
					end if;
				when rx_data_sy_l =>
					if(receive_flag = '1')then
						temp_osd_py(7 downto 0) <= receive_data;
						next_state <= rx_data_effect;
					end if;
				when rx_data_effect =>
					if(receive_flag = '1')then
						temp_osd_command <= receive_data;
						if(receive_data = X"14")then
							next_state <= rx_transparency;
						else
							next_state <= rx_data_end;
						end if;
					end if;
				when rx_transparency =>
					if(receive_flag = '1')then
						temp_transparency <= receive_data;
						next_state <= rx_transparency_end;
					end if;
				when rx_transparency_end =>
					if(receive_flag = '1')then
						if(receive_data = X"03")then
							if(data_no(4 downto 3) = "00")then
								transparency <= temp_transparency;
							elsif(data_no(4 downto 3) = "01")then
								transparency1 <= temp_transparency;
							elsif(data_no(4 downto 3) = "10")then
								transparency2 <= temp_transparency;
							else
								transparency3 <= temp_transparency;
							end if;
						end if;
						next_state <= idle;
					end if;
				when rx_data_end =>
					if(receive_flag = '1')then
						if(receive_data = X"03")then
							length_address <= data_no(4 downto 0);
							next_state <= rx_data_length;
						else
							next_state <= idle;
						end if;
					end if;
				when rx_data_length =>
					next_state <= rx_data_length_end;
				when rx_data_length_end =>
					if(data_no(4 downto 3) = "00")then
						osd_command <= temp_osd_command;
						if(temp_osd_command /= "00000000")then
							osd_data_no <= data_no;
							osd_px <= temp_osd_px(12 downto 0);
							osd_py <= temp_osd_py(10 downto 0);
							osd_dx <= length_q(21 downto 10);
							osd_dy <= length_q(9 downto 0);
						end if;
					elsif(data_no(4 downto 3) = "01")then
						osd1_command <= temp_osd_command;
						if(temp_osd_command /= "00000000")then
							osd1_data_no <= data_no;
							osd1_px <= temp_osd_px(12 downto 0);
							osd1_py <= temp_osd_py(10 downto 0);
							osd1_dx <= length_q(21 downto 10);
							osd1_dy <= length_q(9 downto 0);
						end if;
					elsif(data_no(4 downto 3) = "10")then
						osd2_command <= temp_osd_command;
						if(temp_osd_command /= "00000000")then
							osd2_data_no <= data_no;
							osd2_px <= temp_osd_px(12 downto 0);
							osd2_py <= temp_osd_py(10 downto 0);
							osd2_dx <= length_q(21 downto 10);
							osd2_dy <= length_q(9 downto 0);
						end if;
					else
						osd3_command <= temp_osd_command;
						if(temp_osd_command /= "00000000")then
							osd3_data_no <= data_no;
							osd3_px <= temp_osd_px(12 downto 0);
							osd3_py <= temp_osd_py(10 downto 0);
							osd3_dx <= length_q(21 downto 10);
							osd3_dy <= length_q(9 downto 0);
						end if;
					end if;
					next_state <= idle;
				when rx_data_dx_h =>
					if(receive_flag = '1')then
						temp_osd_dx(15 downto 8) <= receive_data;
						next_state <= rx_data_dx_l;
					end if;
				when rx_data_dx_l =>
					if(receive_flag = '1')then
						temp_osd_dx(7 downto 0) <= receive_data;
						next_state <= rx_data_dy_h;
					end if;
				when rx_data_dy_h =>
					if(receive_flag = '1')then
						temp_osd_dy(15 downto 8) <= receive_data;
						next_state <= rx_data_dy_l;
					end if;
				when rx_data_dy_l =>
					if(receive_flag = '1')then
						temp_osd_dy(7 downto 0) <= receive_data;
						next_state <= rx_data_image;
					end if;
				when rx_data_image =>
					dx_count <= temp_osd_dx(14 downto 0) & '0';
					dy_count <= temp_osd_dy;
					address_count <= (others => '0');
					byte_count <= (others => '0');
					delay_count <= (others => '0');
					next_state <= rx_data_image_count;
				when rx_data_image_count =>
					length_wren <= '0';
					if(receive_flag = '1')then
						delay_count <= (others => '0');
						case byte_count is
							when "0000" =>
								image_data(7 downto 0) <= receive_data;
							when "0001" =>
								image_data(15 downto 8) <= receive_data;
							when "0010" =>
								image_data(23 downto 16) <= receive_data;
							when "0011" =>
								image_data(31 downto 24) <= receive_data;
							when "0100" =>
								image_data(39 downto 32) <= receive_data;
							when "0101" =>
								image_data(47 downto 40) <= receive_data;
							when "0110" =>
								image_data(55 downto 48) <= receive_data;
							when "0111" =>
								image_data(63 downto 56) <= receive_data;
							when "1000" =>
								image_data(71 downto 64) <= receive_data;
							when "1001" =>
								image_data(79 downto 72) <= receive_data;
							when "1010" =>
								image_data(87 downto 80) <= receive_data;
							when "1011" =>
								image_data(95 downto 88) <= receive_data;
							when "1100" =>
								image_data(103 downto 96) <= receive_data;
							when "1101" =>
								image_data(111 downto 104) <= receive_data;
							when "1110" =>
								image_data(119 downto 112) <= receive_data;
							when others =>
								image_data(127 downto 120) <= receive_data;
						end case;
						if(dx_count = "0000000000000001")then
							dx_count <= temp_osd_dx(14 downto 0) & '0';
							if(dy_count = "0000000000000001")then
								byte_count <= "1111";
							end if;
							dy_count <= dy_count - 1;
						else
							dx_count <= dx_count - 1;
						end if;
						next_state <= rx_data_image_count1;
					else
						if(delay_count = "11111111111111111111111111")then
							delay_count <= (others => '0');
							next_state <= idle;
						else
							delay_count <= delay_count + 1;
						end if;
					end if;
				when rx_data_image_count1 =>
					if(byte_count = "1111")then
						image_address <= data_no(4 downto 0) & address_count & "000";
						image_wrreq <= '1';
						address_count <= address_count + 1;
						next_state <= rx_data_image_end;
					else
						next_state <= rx_data_image_count;
					end if;
					byte_count <= byte_count + 1;
				when rx_data_image_end =>
					if(image_wrack = '1')then
						image_wrreq <= '0';
						if(dy_count = "0000000000000000")then
							next_state <= rx_data_image_stop;
						else
							next_state <= rx_data_image_count;
						end if;
					end if;
				when rx_data_image_stop =>
					if(receive_flag = '1')then
						if(receive_data = X"03")then
							length_address <= data_no(4 downto 0);
							length_data <= temp_osd_dx(11 downto 0) & temp_osd_dy(9 downto 0);
							length_wren <= '1';
						end if;
						next_state <= idle;
					end if;
			end case;
		end if;
		current_state <= next_state;
	end process;
end command_receiver_a;