command_receiver.vhd

infra pen controller, cmos sensor control and sdram control

--============================================================================
-- Project 		: On Screen Display
-- Programmer	: Byungchan Son
-- Function		: 
-- Language		: VHDL
--============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--============================================================================
-- 涝免仿 器飘 沥狼
--============================================================================
entity command_receiver is
	port(
		-- system signal
		reset : in std_logic;
		clock : in std_logic;
		-- capture main
		cmd_rx : in std_logic;
		-- sdram control
		image_address : out std_logic_vector(23 downto 0);
		image_data : out std_logic_vector(127 downto 0);
		image_wrreq : out std_logic;
		image_wrack : in std_logic;
		-- osd control signal
		transparency : out std_logic_vector(7 downto 0);
		transparency1 : out std_logic_vector(7 downto 0);
		transparency2 : out std_logic_vector(7 downto 0);
		transparency3 : out std_logic_vector(7 downto 0);
		osd_command : out std_logic_vector(7 downto 0);
		osd_data_no : out std_logic_vector(7 downto 0);
		osd_px : out std_logic_vector(12 downto 0);
		osd_py : out std_logic_vector(10 downto 0);
		osd_dx : out std_logic_vector(11 downto 0);
		osd_dy : out std_logic_vector(9 downto 0);
		osd1_command : out std_logic_vector(7 downto 0);
		osd1_data_no : out std_logic_vector(7 downto 0);
		osd1_px : out std_logic_vector(12 downto 0);
		osd1_py : out std_logic_vector(10 downto 0);
		osd1_dx : out std_logic_vector(11 downto 0);
		osd1_dy : out std_logic_vector(9 downto 0);
		osd2_command : out std_logic_vector(7 downto 0);
		osd2_data_no : out std_logic_vector(7 downto 0);
		osd2_px : out std_logic_vector(12 downto 0);
		osd2_py : out std_logic_vector(10 downto 0);
		osd2_dx : out std_logic_vector(11 downto 0);
		osd2_dy : out std_logic_vector(9 downto 0);
		osd3_command : out std_logic_vector(7 downto 0);
		osd3_data_no : out std_logic_vector(7 downto 0);
		osd3_px : out std_logic_vector(12 downto 0);
		osd3_py : out std_logic_vector(10 downto 0);
		osd3_dx : out std_logic_vector(11 downto 0);
		osd3_dy : out std_logic_vector(9 downto 0)
		);
end command_receiver;
--============================================================================
-- 备炼 沥狼
--============================================================================
architecture command_receiver_a of command_receiver is
--------------------------------------------------------------------
-- 郴何 葛碘
--------------------------------------------------------------------
-- DX,DY
component length_memory IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (21 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (21 DOWNTO 0)
	);
end component;
--------------------------------------------------------------------
-- 郴何 脚龋
--------------------------------------------------------------------
type command_receiver_state is(
	idle,
	rx_code,
	rx_data_no,
	rx_data_sx_h,
	rx_data_sx_l,
	rx_data_sy_h,
	rx_data_sy_l,
	rx_data_effect,
	rx_transparency,
	rx_transparency_end,
	rx_data_end,
	rx_data_length,
	rx_data_length_end,
	rx_data_dx_h,
	rx_data_dx_l,
	rx_data_dy_h,
	rx_data_dy_l,
	rx_data_image,
	rx_data_image_count,
	rx_data_image_count1,
	rx_data_image_end,
	rx_data_image_stop
	);
-- state machine signal
signal current_state, next_state : command_receiver_state;

-- 荐脚 葛碘
type receive_state is(
	rx_ready,
	rx_start,
	rx_data_accept,
	rx_stop_bit
	);
signal rx_current_state, rx_next_state : receive_state;

-- baud rate 努钒 惯积扁
signal rx_baudrate_clock : std_logic;
signal rx_baudrate_clock1 : std_logic;
signal rx_baudrate_counter : std_logic_vector(7 downto 0);
-- 荐脚何 脚龋
signal rx_baudrate_enable : std_logic;
signal sync_rx_line : std_logic;
signal clk1_rx_line : std_logic;
signal rx_buffer : std_logic_vector(7 downto 0);
signal rx_bit_count : std_logic_vector(2 downto 0);
signal rx_data : std_logic_vector(7 downto 0);

-- data signal
signal data_no : std_logic_vector(7 downto 0);
signal data_code : std_logic_vector(7 downto 0);
signal receive_data : std_logic_vector(7 downto 0);
signal receive_flag : std_logic;
signal temp_command : std_logic_vector(15 downto 0);
signal sync_cmd_clk : std_logic;
signal temp_cmd_clk : std_logic;
signal sync_cmd_en : std_logic;
signal temp_cmd_en : std_logic;
signal temp_osd_command : std_logic_vector(7 downto 0);
signal temp_osd_px : std_logic_vector(15 downto 0);
signal temp_osd_py : std_logic_vector(15 downto 0);
signal temp_osd_dx : std_logic_vector(15 downto 0);
signal temp_osd_dy : std_logic_vector(15 downto 0);
signal byte_count : std_logic_vector(3 downto 0);
signal dx_count : std_logic_vector(15 downto 0);
signal dy_count : std_logic_vector(15 downto 0);
signal address_count : std_logic_vector(15 downto 0);
signal delay_count : std_logic_vector(25 downto 0);

constant character_color : std_logic_vector(31 downto 0) := "11010010000100001101001010010010";

-- DX,DY
signal length_address : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal length_data : STD_LOGIC_VECTOR (21 DOWNTO 0);
signal length_wren : STD_LOGIC ;
signal length_q : STD_LOGIC_VECTOR (21 DOWNTO 0);
-- 捧疙档
signal temp_transparency : std_logic_vector(7 downto 0);

--============================================================================
-- 橇肺技辑 矫累
--============================================================================
begin
	----------------------------------------------------------------
	-- 郴何 葛碘 搬急
	----------------------------------------------------------------
	m1 : length_memory
	port map(
		address => length_address,
		clock => clock,
		data => length_data,
		wren => length_wren,
		q => length_q
		);
	----------------------------------------------------------------
	-- baud rate 努钒 惯积扁
	----------------------------------------------------------------
	baudrate_generator : process(
		reset,
		clock,
		rx_baudrate_clock,
		rx_baudrate_counter
		)
	begin
		if(reset = '1')then
			-- 惑怕 扁拌
			-- 郴何 脚龋
			rx_baudrate_clock <= '0';
			rx_baudrate_counter <= (others => '0');
		elsif(clock'event and clock = '1')then
			-- 荐脚 baudrate 努钒 惯积扁
			if(rx_baudrate_enable = '1')then
				if(rx_baudrate_counter = "01000110")then -- 81MHz : 576000
--				if(rx_baudrate_counter = "10011110")then -- 81MHz : 256000
--				if(rx_baudrate_counter = "11000001")then -- 99MHz : 256000
--				if(rx_baudrate_counter = "11010011")then -- 108MHz : 256000
					rx_baudrate_clock <= not rx_baudrate_clock;
                    rx_baudrate_counter <= (others => '0');
				else
					rx_baudrate_counter <= rx_baudrate_counter + 1;
                end if;
			else
				rx_baudrate_counter <= (others => '0');
				rx_baudrate_clock <= '0';
			end if;
		end if;
	end process;
	----------------------------------------------------------------
	-- 荐脚 葛碘
	----------------------------------------------------------------
	receiver : process(
		reset,
		clock,
		cmd_rx,
		sync_rx_line,
		clk1_rx_line,
		rx_current_state,
		rx_next_state,
		rx_baudrate_clock,
		rx_bit_count
		)
	begin
		if(reset = '1')then
			-- 惑怕 扁拌
			rx_next_state <= rx_ready;
			-- 郴何 脚龋
			rx_buffer <= (others => '0');
			rx_bit_count <= (others => '0');
			rx_baudrate_enable <= '0';
			rx_baudrate_clock1 <= '0';
			receive_data <= (others => '0');
		elsif(clock'event and clock = '1')then
			sync_rx_line <= cmd_rx;
			clk1_rx_line <= sync_rx_line;
			rx_baudrate_clock1 <= rx_baudrate_clock;
			case rx_current_state is
				when rx_ready =>
					receive_flag <= '0';
					if(clk1_rx_line = '1' and sync_rx_line = '0')then
						rx_baudrate_enable <= '1';
						rx_next_state <= rx_start;
					else
						rx_baudrate_enable <= '0';
					end if;
				when rx_start =>
					if(rx_baudrate_clock1 = '0' and rx_baudrate_clock = '1')then
						if(sync_rx_line = '0')then
							rx_next_state <= rx_data_accept;
						else
							rx_next_state <= rx_ready;
						end if;
					end if;
				when rx_data_accept =>
					if(rx_baudrate_clock1 = '0' and rx_baudrate_clock = '1')then
						rx_buffer(7) <= sync_rx_line;
						rx_buffer(6) <= rx_buffer(7);
						rx_buffer(5) <= rx_buffer(6);
						rx_buffer(4) <= rx_buffer(5);
						rx_buffer(3) <= rx_buffer(4);
						rx_buffer(2) <= rx_buffer(3);
						rx_buffer(1) <= rx_buffer(2);
						rx_buffer(0) <= rx_buffer(1);
						if(rx_bit_count = "111")then
							rx_bit_count <= (others => '0');
							rx_next_state <= rx_stop_bit;
						else
							rx_bit_count <= rx_bit_count + 1;
						end if;
					end if;
				when rx_stop_bit =>
					if(rx_baudrate_clock1 = '0' and rx_baudrate_clock = '1')then
						if(sync_rx_line = '1')then
							receive_data <= rx_buffer;
							receive_flag <= '1';
							--rx_data <= rx_buffer;
						end if;
						rx_next_state <= rx_ready;
					end if;
			end case;
		end if;
		rx_current_state <= rx_next_state;
	end process;
	----------------------------------------------------------------
	-- 皋牢 橇肺技辑
	----------------------------------------------------------------
	-- 疙飞 荐脚
	main : process(
		reset,
		clock,
		current_state,
		next_state,
		receive_flag,
		data_code,
		receive_data,
		byte_count,
		dx_count,