📄 sdram_control.vhd
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--============================================================================
-- Project : On Screen Display
-- Programmer : Byungchan Son
-- Function :
-- Language : VHDL
--============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--============================================================================
-- 涝免仿 器飘 沥狼
--============================================================================
entity sdram_control is
port(
-- system signal
reset : in std_logic;
clock : in std_logic;
-- capture main : sdram signal
sda : out std_logic_vector(12 downto 0);
sdd_in : in std_logic_vector(15 downto 0);
sdd_out : out std_logic_vector(15 downto 0);
sdd_hz : out std_logic;
sdba : out std_logic_vector(1 downto 0);
sdqm : out std_logic_vector(1 downto 0);
sdcas : out std_logic;
sdras : out std_logic;
sdwe : out std_logic;
sdcs : out std_logic;
-- sdcke : out std_logic;
sdclk : out std_logic;
-- cmos control
buff_data : in std_logic_vector(127 downto 0);
buff_wrreq : in std_logic;
buff_rdreq : in std_logic;
buff_rdack : out std_logic;
buff_acer : in std_logic;
buff_reset : in std_logic;
pos_image_address : in std_logic_vector(23 downto 0);
pos_image_read_req : in std_logic;
pos_image_read_ack : out std_logic;
-- uart
image_data : out std_logic_vector(127 downto 0)
-- test signal
);
end sdram_control;
--============================================================================
-- 备炼 沥狼
--============================================================================
architecture sdram_control_a of sdram_control is
--------------------------------------------------------------------
-- 郴何 葛碘
--------------------------------------------------------------------
component data_buff
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
end component;
--------------------------------------------------------------------
-- 郴何 脚龋
--------------------------------------------------------------------
type sdram_control_state is(
mode_ready,
precharge_set,
precharge_set1,
autorefresh_set,
autorefresh_set1,
mode_set,
mode_set1,
idle,
read_buff,
read_buff_end,
check_refresh,
refresh_cycle,
read_ras,
read_ras_delay,
read_ras_delay1,
read_cas,
read_cas_delay1,
read_cas_delay2,
read_cas_delay3,
read_data0,
read_data1,
read_data2,
read_data3,
read_data4,
read_data5,
read_data6,
read_data7,
read_end_ready,
read_end,
read_end_1,
write_ras,
write_cas,
write_data1,
write_data2,
write_data3,
write_data4,
write_data5,
write_data6,
write_data7,
write_precharge_ready1,
write_precharge_ready2,
write_end
);
-- state machine signal
signal current_state, next_state : sdram_control_state;
-- data signal
signal sdram_address : std_logic_vector(23 downto 0);
signal pixel_data_rd : std_logic_vector(127 downto 0);
signal pixel_data_wr : std_logic_vector(127 downto 0);
signal refresh_count : std_logic_vector(5 downto 0);
signal refresh_flag : std_logic;
signal reset_count : std_logic_vector(15 downto 0);
signal fifo_rdreq : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_q : std_logic_vector(127 downto 0);
signal image_address : std_logic_vector(23 downto 0);
signal read_flag : std_logic;
-- 闰祸
--constant character_color : std_logic_vector(31 downto 0) := "10000000111010111000000011101011";
-- 畴鄂祸
--constant character_color1 : std_logic_vector(31 downto 0) := "00010000110100101001001011010010";
--============================================================================
-- 橇肺技辑 矫累
--============================================================================
begin
----------------------------------------------------------------
-- 郴何 葛碘 搬急
----------------------------------------------------------------
m1 : data_buff
port map(
aclr => buff_acer,
clock => clock,
data => buff_data,
rdreq => fifo_rdreq,
wrreq => buff_wrreq,
empty => fifo_empty,
full => fifo_full,
q => fifo_q
);
----------------------------------------------------------------
-- 皋牢 橇肺技辑
----------------------------------------------------------------
process(
reset,
clock,
current_state,
next_state,
reset_count,
refresh_count,
fifo_empty,
buff_rdreq,
buff_reset,
refresh_flag
)
begin
sdclk <= clock;
if(reset = '1')then
next_state <= mode_ready;
sdqm <= "11";
sdcas <= '0';
sdras <= '0';
sdwe <= '0';
sdcs <= '0';
sdba <= "00";
sda <= (others => '0');
sdd_hz <= '1';
refresh_count <= (others => '0');
reset_count <= (others => '0');
sdram_address <= (others => '0');
image_address <= (others => '0');
pixel_data_rd <= (others => '0');
pixel_data_wr <= (others => '0');
refresh_flag <= '1';
pos_image_read_ack <= '0';
read_flag <= '0';
elsif(clock'event and clock = '1')then
case current_state is
when mode_ready =>
if(reset_count = "1111111111111111")then
reset_count <= (others => '0');
next_state <= precharge_set;
else
reset_count <= reset_count + 1;
end if;
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
sdba <= "00";
sdqm <= "11";
when precharge_set =>
sdras <= '1';
sdcas <= '0';
sdwe <= '1';
sdcs <= '1';
-- sdba <= "00";
-- sdqm <= "00";
sda(10) <= '1';
next_state <= precharge_set1;
when precharge_set1 =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
if(refresh_count = "000011")then
refresh_count <= (others => '0');
next_state <= autorefresh_set;
else
refresh_count <= refresh_count + 1;
end if;
when autorefresh_set =>
sdras <= '1';
sdcas <= '1';
sdwe <= '0';
sdcs <= '1';
next_state <= autorefresh_set1;
when autorefresh_set1 =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
if(refresh_count = "000011")then
refresh_count <= (others => '0');
next_state <= mode_set;
else
refresh_count <= refresh_count + 1;
end if;
when mode_set =>
sdras <= '1';
sdcas <= '1';
sdwe <= '1';
sdcs <= '1';
sdba <= "00";
sdqm <= "00";
sda <= "0000000110011";
next_state <= mode_set1;
when mode_set1 =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
if(refresh_count = "000011")then
refresh_count <= (others => '0');
next_state <= idle;
else
refresh_count <= refresh_count + 1;
end if;
when idle =>
-- 磊阜 钎矫
if(fifo_empty = '0')then
fifo_rdreq <= '1';
next_state <= read_buff;
elsif(buff_rdreq = '1')then
sdram_address <= image_address;
image_address <= image_address + 8;
next_state <= read_ras;
read_flag <= '0';
elsif(buff_reset = '1')then
image_address <= (others => '0');
elsif(pos_image_read_req = '1')then
read_flag <= '1';
-- sdram_address <= pos_image_address(22 downto 0) & '0';
sdram_address <= pos_image_address;
next_state <= read_ras;
else
next_state <= check_refresh;
end if;
sdd_hz <= '1';
when read_buff =>
fifo_rdreq <= '0';
next_state <= read_buff_end;
when read_buff_end =>
sdram_address <= image_address;
image_address <= image_address + 8;
pixel_data_wr <= fifo_q;
next_state <= write_ras;
when check_refresh =>
if(refresh_flag = '1')then
refresh_flag <= '0';
sdras <= '1';
sdcas <= '1';
sdwe <= '0';
sdcs <= '1';
next_state <= refresh_cycle;
else
if(reset_count = "1111111111111111")then
reset_count <= (others => '0');
refresh_flag <= '1';
else
reset_count <= reset_count + 1;
end if;
next_state <= idle;
end if;
when refresh_cycle =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
if(refresh_count = "000111")then
refresh_count <= (others => '0');
next_state <= idle;
else
refresh_count <= refresh_count + 1;
end if;
when read_ras =>
sdras <= '1';
sdcas <= '0';
sdwe <= '0';
sdcs <= '1';
sdba <= sdram_address(23 downto 22);
sda <= sdram_address(21 downto 9);
sdd_hz <= '1';
next_state <= read_ras_delay;
when read_ras_delay =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
next_state <= read_ras_delay1;
when read_ras_delay1 =>
next_state <= read_cas;
when read_cas =>
sdras <= '0';
sdcas <= '1';
sdwe <= '0';
sdcs <= '1';
sda <= "0000" & sdram_address(8 downto 3) & "000";
next_state <= read_cas_delay1;
when read_cas_delay1 =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
next_state <= read_cas_delay2;
when read_cas_delay2 =>
next_state <= read_cas_delay3;
when read_cas_delay3 =>
next_state <= read_data0;
when read_data0 =>
pixel_data_rd(15 downto 0) <= sdd_in;
next_state <= read_data1;
when read_data1 =>
pixel_data_rd(31 downto 16) <= sdd_in;
next_state <= read_data2;
when read_data2 =>
pixel_data_rd(47 downto 32) <= sdd_in;
next_state <= read_data3;
when read_data3 =>
pixel_data_rd(63 downto 48) <= sdd_in;
next_state <= read_data4;
when read_data4 =>
pixel_data_rd(79 downto 64) <= sdd_in;
next_state <= read_data5;
when read_data5 =>
pixel_data_rd(95 downto 80) <= sdd_in;
next_state <= read_data6;
when read_data6 =>
pixel_data_rd(111 downto 96) <= sdd_in;
next_state <= read_data7;
when read_data7 =>
sdras <= '1';
sdcas <= '0';
sdwe <= '1';
sdcs <= '1';
sda(10) <= '0';
pixel_data_rd(127 downto 112) <= sdd_in;
next_state <= read_end_ready;
when read_end_ready =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
image_data <= pixel_data_rd;
if(read_flag = '0')then
buff_rdack <= '1';
next_state <= read_end;
else
pos_image_read_ack <= '1';
next_state <= read_end_1;
end if;
when read_end =>
if(buff_rdreq = '0')then
buff_rdack <= '0';
refresh_flag <= '1';
next_state <= idle;
end if;
when read_end_1 =>
if(pos_image_read_req = '0')then
pos_image_read_ack <= '0';
refresh_flag <= '1';
next_state <= idle;
end if;
-- 8 byte 滚胶飘 静扁
when write_ras =>
sdras <= '1';
sdcas <= '0';
sdwe <= '0';
sdcs <= '1';
sdba <= sdram_address(23 downto 22);
sda <= sdram_address(21 downto 9);
next_state <= write_cas;
when write_cas =>
sdras <= '0';
sdcas <= '1';
sdwe <= '1';
sdcs <= '1';
sda <= "0000" & sdram_address(8 downto 0);
sdd_out <= pixel_data_wr(15 downto 0);
sdd_hz <= '0';
next_state <= write_data1;
when write_data1 =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
sdd_out <= pixel_data_wr(31 downto 16);
sdd_hz <= '0';
next_state <= write_data2;
when write_data2 =>
sdd_out <= pixel_data_wr(47 downto 32);
sdd_hz <= '0';
next_state <= write_data3;
when write_data3 =>
sdd_out <= pixel_data_wr(63 downto 48);
sdd_hz <= '0';
next_state <= write_data4;
when write_data4 =>
sdd_out <= pixel_data_wr(79 downto 64);
sdd_hz <= '0';
next_state <= write_data5;
when write_data5 =>
sdd_out <= pixel_data_wr(95 downto 80);
sdd_hz <= '0';
next_state <= write_data6;
when write_data6 =>
sdd_out <= pixel_data_wr(111 downto 96);
sdd_hz <= '0';
next_state <= write_data7;
when write_data7 =>
sdd_out <= pixel_data_wr(127 downto 112);
sdd_hz <= '0';
next_state <= write_precharge_ready1;
when write_precharge_ready1 =>
next_state <= write_precharge_ready2;
when write_precharge_ready2 =>
sdras <= '1';
sdcas <= '0';
sdwe <= '1';
sdcs <= '1';
sda(10) <= '0';
next_state <= write_end;
when write_end =>
sdras <= '0';
sdcas <= '0';
sdwe <= '0';
sdcs <= '0';
sdd_hz <= '1';
refresh_flag <= '1';
next_state <= idle;
end case;
end if;
current_state <= next_state;
end process;
----------------------------------------------------------------
-- 肺流 脚龋
----------------------------------------------------------------
end sdram_control_a;
--============================================================================
-- 场
--============================================================================
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