lcd_display.vhd

lcd_display use vhdl in fpga

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:26:34 03/18/2009 
-- Design Name: 
-- Module Name:    lcd_display - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--package my_signal is
--	signal substate,clock,state : integer :=0;
--end my_signal;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.my_signal.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd_display is
--	 Generic (signal substate,clock,state : integer);
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
			  up_down : in STD_LOGIC;
           cout : out  STD_LOGIC_VECTOR (7 downto 0);
           e : out  STD_LOGIC;
           rs : out  STD_LOGIC;
           rw : out  STD_LOGIC;
           d : inout  STD_LOGIC_VECTOR (3 downto 0));
end lcd_display;

architecture Behavioral of lcd_display is

signal count : std_logic_vector(7 downto 0);
signal i,j,k,l : integer:=0;
signal state,clock,substate: integer:=0;
signal e_0,rs_0,rw_0 : std_logic;
signal d_0 : std_logic_vector(3 downto 0);
signal x,y,z : std_logic_vector(7 downto 0);

procedure ghi ( signal e_0,rs_0,rw_0 : out STD_LOGIC;
					 signal d_0 : inout STD_LOGIC_VECTOR (3 downto 0);
					 x : in integer;
					 y : in STD_LOGIC_VECTOR (7 downto 0);
					 z : in integer;
					 signal clock_0 : inout integer;
					 signal state_0 : inout integer)  is
variable substate : integer :=0;

	begin
		
			if(substate=0 and clock_0=0) then
                if x = 0 then rs_0 <= '0';		--x=0 ghi lenh, x=1 ghi du lieu
					 else rs_0 <= '1';end if;
					 e_0<='0';
                rw_0<='0';
                d_0<=y(7 downto 4);
                clock_0<=0;
                substate:=1;
         elsif(substate=1 and clock_0=5) then
                e_0<='1';
                clock_0<=0;
                substate:=2;
         elsif(substate=2 and clock_0=12) then
                e_0<='0';
                substate:=3;
                clock_0<=0;
         elsif(substate=3 and clock_0=48) then
                d_0<=y(3 downto 0);
                clock_0<=0;
                substate:=4;
         elsif(substate=4 and clock_0=5) then
                e_0<='1';   
                clock_0<=0;
                substate:=5;
         elsif(substate=5 and clock_0=12) then
                e_0<='0';
                substate:=0;
                clock_0<= 0;
					 state_0<= z;
         end if;
end procedure ghi;

function doi(x : in integer) return std_logic_vector is
	variable result : std_logic_vector (7 downto 0);
	begin
		case x is
			when 0 => result := X"30";
			when 1 => result := X"31";
			when 2 => result := X"32";
			when 3 => result := X"33";
			when 4 => result := X"34";
			when 5 => result := X"35";
			when 6 => result := X"36";
			when 7 => result := X"37";
			when 8 => result := X"38";
			when 9 => result := X"39";
			when others => null;
		end case;
	return (result);
	end doi;



begin
	
	
	process (clk,reset)
--	port map (e => e_0,rs => rs_0,rw => rw_0,d => d_0);		
	begin
	if (reset = '1') then 
			count <=(others=>'0');
			j <= 0;
--			e <= '0';
			clock <= 0;
	elsif clk = '1' and clk' event then
		clock <= clock +1;
		if(state=0 and clock=750000) then
				e_0 <= '0';
            state<=1;
            clock<=0;
		elsif(state=1) then
--		y<= "00000011";
			if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="0011";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<= 2;
         end if;
			
			
		elsif(state=2 and clock=205000) then
            state<=3;
            clock<=0;
		elsif(state=3) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="0011";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<= 4;
         end if;
		elsif(state=4 and clock=5000) then
            state<=5;
            clock<=0;
		elsif(state=5) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="0011";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<= 6;
         end if;
		elsif(state=6 and clock=2000) then
            state<=7;
            clock<=0;
		elsif(state=7) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="0001";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<= 8;
         end if;
		elsif(state=8 and clock=2000) then
            state<=9;
            clock<=0;
		elsif(state=9) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0010";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="1000";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<= 10;
         end if;
		elsif(state=10 and clock=2000) then
            state<=11;
            clock<=0;
		elsif(state=11) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="0110";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<= 12;
         end if;
		elsif(state=12 and clock=2000) then
            state<=13;
            clock<=0;
		elsif(state=13) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="1100";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<=14;
         end if;
		elsif(state=14 and clock=2000) then
            state<=15;
            clock<=0;
		elsif(state=15) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="0000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="0001";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<= 16;
         end if;
		elsif(state=16 and clock=82000) then
            state<=17;
            clock<=0;
		elsif(state=17) then
		if(substate=0 and clock=0) then 
					 rs<='0';
					 e<='0';
                rw<='0';
                d<="1000";
                clock<=0;
                substate<=1;
         elsif(substate=1 and clock=5) then
                e<='1';
                clock<=0;
                substate<=2;
         elsif(substate=2 and clock=12) then
                e<='0';
                substate<=3;
                clock<=0;
         elsif(substate=3 and clock=48) then
                d<="0000";
                clock<=0;
                substate<=4;
         elsif(substate=4 and clock=5) then
                e<='1';   
                clock<=0;
                substate<=5;
         elsif(substate=5 and clock=12) then
                e<='0';
                substate<=0;
                clock<= 0;
					 state<=18;
         end if;
		
		elsif(state=18 and clock=2000) then
            state<=19;
            clock<=0;		
				
				
		elsif(state=19) then
		
		i <= i + 1;
			if (i >= 2500000) then
					if (up_down = '1')then
						count<=count + 1;
						j <= j +1;
							if (j= 9) then 
								j<=0;
								k<=k+1;
								if (k=9) then	
									k<=0;
									l<=l+1;
								end if;
							end if;
					else count<= count -1;
						j <= j -1;
							if (j= 0) then 
								j<=9;
								k<=k-1;
								if (k=0) then	
									k<=9;
									l<=l-1;
								end if;
							end if;
					end if;
					i <= 0;
			end if;
		
		x<=doi(j);
		y<=doi(k);
		z<=doi(l);
		
		
--		if(substate=0 and clock=0) then 
--					 rs<='1';
--					 e<='0';
--                rw<='0';
--                d<=x(7 downto 4);
--                clock<=0;
--                substate<=1;
--         elsif(substate=1 and clock=5) then
--                e<='1';
--                clock<=0;
--                substate<=2;
--         elsif(substate=2 and clock=12) then
--                e<='0';
--                substate<=3;
--                clock<=0;
--         elsif(substate=3 and clock=48) then
--                d<=x(3 downto 0);
--                clock<=0;
--                substate<=4;
--         elsif(substate=4 and clock=5) then
--                e<='1';   
--                clock<=0;
--                substate<=5;
--         elsif(substate=5 and clock=12) then
--                e<='0';
--                substate<=0;
--                clock<= 0;
--					 state<= 17;
--         end if;
			
		
--		ghi(e,rs,rw,d,'1',doi((j - (j mod 100)*100) mod 10),19,clock,state);
--		ghi(e,rs,rw,d,'1',doi((j - (j mod 100)*100)- ((j - (j mod 100)*100) mod 10)*10),19,clock,state);
		
			
		end if;
--	end if;
	end if;
	cout <= count;
	end process;
	
end Behavioral;