📄 wuxinkun.rpt
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Project Information h:\ex1\wuxinkun.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/24/2009 19:25:11
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
wuxinkun EPM7096LC68-7 10 9 0 66 20 68 %
User Pins: 10 9 0
Project Information h:\ex1\wuxinkun.rpt
** FILE HIERARCHY **
|7483:31|
|7483:34|
|7483:33|
|7483:32|
Device-Specific Information: h:\ex1\wuxinkun.rpt
wuxinkun
***** Logic for device 'wuxinkun' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R
E E E E
V S S S S
C E E V E E
C R R C R R
G I G G G G G V V C V V
A A B N B B N N N N N N E E I E E
0 3 3 D 0 2 T D D D D D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
A2 | 10 60 | RESERVED
VCCIO | 11 59 | RESERVED
A1 | 12 58 | GND
B1 | 13 57 | P6
RESERVED | 14 56 | RESERVED
RESERVED | 15 55 | RESERVED
GND | 16 54 | RESERVED
RESERVED | 17 53 | VCCIO
RESERVED | 18 EPM7096LC68-7 52 | RESERVED
RESERVED | 19 51 | RESERVED
P2 | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
BS | 22 48 | GND
AS | 23 47 | P7
RESERVED | 24 46 | RESERVED
RESERVED | 25 45 | P3
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
R P R P V R R G V R R G P P P R V
E 0 E S C E E N C E E N 5 4 1 E C
S S C S S D C S S D S C
E E I E E I E E E I
R R O R R N R R R O
V V V V T V V V
E E E E E E E
D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: h:\ex1\wuxinkun.rpt
wuxinkun
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 8/ 8(100%) 1/16( 6%) 9/36( 25%)
B: LC17 - LC32 2/16( 12%) 3/ 8( 37%) 5/16( 31%) 10/36( 27%)
C: LC33 - LC48 16/16(100%) 2/ 8( 25%) 15/16( 93%) 18/36( 50%)
D: LC49 - LC64 16/16(100%) 4/ 8( 50%) 16/16(100%) 24/36( 66%)
E: LC65 - LC80 16/16(100%) 1/ 8( 12%) 16/16(100%) 21/36( 58%)
F: LC81 - LC96 15/16( 93%) 1/ 8( 12%) 15/16( 93%) 33/36( 91%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 19/48 ( 39%)
Total logic cells used: 66/96 ( 68%)
Total shareable expanders used: 20/96 ( 20%)
Total Turbo logic cells used: 66/96 ( 68%)
Total shareable expanders not available (n/a): 48/96 ( 50%)
Average fan-in: 8.89
Total fan-in: 587
Total input pins required: 10
Total output pins required: 9
Total bidirectional pins required: 0
Total logic cells required: 66
Total flipflops required: 0
Total product terms required: 298
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 17
Synthesized logic cells: 55/ 96 ( 57%)
Device-Specific Information: h:\ex1\wuxinkun.rpt
wuxinkun
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
23 (17) (B) INPUT 0 0 0 0 0 1 0 AS
9 (8) (A) INPUT 0 0 0 0 0 8 48 A0
12 (4) (A) INPUT 0 0 0 0 0 5 54 A1
10 (6) (A) INPUT 0 0 0 0 0 4 51 A2
8 (9) (A) INPUT 0 0 0 0 0 3 51 A3
22 (19) (B) INPUT 0 0 0 0 0 1 0 BS
5 (14) (A) INPUT 0 0 0 0 0 5 50 B0
13 (1) (A) INPUT 0 0 0 0 0 4 49 B1
4 (16) (A) INPUT 0 0 0 0 0 6 49 B2
7 (12) (A) INPUT 0 0 0 0 0 5 36 B3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: h:\ex1\wuxinkun.rpt
wuxinkun
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
30 37 C OUTPUT t 0 0 0 2 0 0 0 PS
28 41 C OUTPUT t 0 0 0 2 0 0 0 P0
41 57 D OUTPUT t 0 0 0 4 0 0 0 P1
20 21 B OUTPUT t 3 2 1 6 1 0 0 P2
45 64 D OUTPUT t 1 0 0 3 2 0 0 P3
40 56 D OUTPUT t 4 0 0 8 7 0 0 P4
39 53 D OUTPUT t 1 0 0 4 8 0 0 P5
57 84 F OUTPUT t 6 3 0 8 25 0 0 P6
47 67 E OUTPUT t 2 0 0 5 11 0 0 P7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: h:\ex1\wuxinkun.rpt
wuxinkun
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(36) 49 D SOFT t 0 0 0 6 0 2 35 |7483:32|C4 (|7483:32|:83)
(61) 89 F SOFT s t 0 0 0 0 2 0 1 |7483:33|~2~1
(42) 59 D SOFT s t 1 0 1 7 1 1 3 |7483:33|~2~2
- 42 C SOFT s t 1 0 1 7 1 1 3 |7483:33|~2~3
- 18 B SOFT s t 3 1 1 7 2 4 17 |7483:33|~29~1
- 34 C SOFT s t 1 0 1 7 0 0 1 |7483:33|~29~2
(32) 35 C SOFT s t 1 0 1 6 0 0 1 |7483:33|~29~3
(44) 61 D SOFT s t 0 0 0 6 0 1 0 |7483:33|S1~1 (|7483:33|~42~1)
- 90 F SOFT t 0 0 0 0 2 1 5 |7483:33|C4 (|7483:33|:83)
- 66 E SOFT s t 1 0 1 8 4 1 0 |7483:34|~2~2
- 68 E SOFT s t 1 0 1 8 4 1 0 |7483:34|~2~3
- 70 E SOFT s t 1 0 1 8 4 1 0 |7483:34|~2~4
(51) 73 E SOFT s t 1 0 1 8 4 1 0 |7483:34|~2~5
- 74 E SOFT s t 1 0 1 8 4 1 0 |7483:34|~2~6
(52) 75 E SOFT s t 1 0 1 8 7 1 0 |7483:34|~2~7
- 95 F SOFT s t 2 2 0 5 6 0 3 |7483:34|~21~1
(56) 81 F SOFT s t 1 0 1 8 1 1 2 |7483:34|~21~2
- 83 F SOFT s t 1 0 1 8 1 1 2 |7483:34|~21~3
(65) 96 F SOFT s t 1 0 1 8 1 1 1 |7483:34|~21~4
(37) 51 D SOFT s t 1 0 1 7 1 1 2 |7483:34|~21~5
- 87 F SOFT s t 0 0 0 7 1 1 1 |7483:34|~21~6
- 85 F SOFT s t 0 0 0 2 2 2 6 |7483:34|~22~1
- 36 C SOFT s t 2 2 0 5 7 1 6 |7483:34|~34~1
- 71 E SOFT s t 1 0 1 8 2 0 1 |7483:34|~34~2
(50) 72 E SOFT s t 1 0 1 8 2 0 1 |7483:34|~34~3
(55) 80 E SOFT s t 1 0 1 7 2 0 1 |7483:34|~34~4
(24) 48 C SOFT s t 1 0 1 7 0 1 0 |7483:34|S1~1 (|7483:34|~42~1)
(25) 45 C SOFT s t 1 0 1 8 0 1 0 |7483:34|S2~1 (|7483:34|~43~1)
- 46 C SOFT s t 1 0 1 8 0 1 0 |7483:34|S2~2 (|7483:34|~43~2)
- 47 C SOFT s t 1 0 1 8 0 1 0 |7483:34|S2~3 (|7483:34|~43~3)
- 38 C SOFT s t 1 0 1 8 0 1 0 |7483:34|S2~4 (|7483:34|~43~4)
- 39 C SOFT s t 1 0 1 8 0 1 0 |7483:34|S2~5 (|7483:34|~43~5)
- 55 D SOFT s t 1 0 1 7 1 1 0 |7483:34|S2~6 (|7483:34|~43~6)
(62) 92 F SOFT s t 1 0 1 8 1 1 0 |7483:34|S3~1 (|7483:34|~44~1)
(59) 86 F SOFT s t 1 0 1 8 1 1 0 |7483:34|S3~2 (|7483:34|~44~2)
(33) 33 C SOFT s t 1 0 1 6 2 1 0 |7483:34|S3~3 (|7483:34|~44~3)
- 82 F SOFT s t 1 0 1 8 1 1 0 |7483:34|S3~4 (|7483:34|~44~4)
- 44 C SOFT s t 1 0 1 5 2 1 0 |7483:34|S3~5 (|7483:34|~44~5)
- 60 D SOFT s t 1 0 1 7 1 1 0 |7483:34|S3~6 (|7483:34|~44~6)
(27) 43 C SOFT s t 1 0 1 7 2 1 0 |7483:34|S3~7 (|7483:34|~44~7)
- 91 F SOFT s t 1 0 1 7 2 1 0 |7483:34|~45~1~2
(54) 77 E SOFT s t 1 0 1 7 2 1 0 |7483:34|~45~1~3
- 76 E SOFT s t 1 0 1 7 2 1 0 |7483:34|~45~1~4
- 50 D SOFT s t 1 0 1 6 2 1 0 |7483:34|~45~1~5
(49) 69 E SOFT s t 1 0 1 7 2 1 0 |7483:34|~45~1~6
- 52 D SOFT s t 1 0 1 6 2 1 0 |7483:34|~45~1~7
- 79 E SOFT s t 1 0 1 7 2 1 0 |7483:34|~45~1~8
- 63 D SOFT s t 1 0 1 7 2 1 0 |7483:34|~45~1~9
(64) 94 F SOFT s t 1 0 1 8 2 1 0 |7483:34|~45~1~10
- 93 F SOFT s t 1 0 1 8 2 1 0 |7483:34|~45~1~11
- 62 D SOFT s t 1 0 1 7 2 1 0 |7483:34|~45~1~12
- 5 A SOFT s t 1 0 0 4 5 1 6 |7483:34|~52~1
- 54 D SOFT s t 1 0 1 8 1 1 1 |7483:34|~52~2
(29) 40 C SOFT s t 1 0 1 8 0 1 1 |7483:34|~52~3
- 58 D SOFT s t 1 0 1 7 1 1 1 |7483:34|~52~4
- 78 E SOFT s t 1 0 1 7 2 0 1 |7483:34|~52~5
(46) 65 E SOFT s t 0 0 0 7 0 1 1 |7483:34|~52~6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: h:\ex1\wuxinkun.rpt
wuxinkun
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC5 |7483:34|~52~1
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D E F | Logic cells that feed LAB 'A':
Pin
12 -> * | * * * * * * | <-- A1
10 -> * | * * * * * * | <-- A2
13 -> * | * * * * * * | <-- B1
7 -> * | * - * * * * | <-- B3
LC54 -> * | * - - - - * | <-- |7483:34|~52~2
LC40 -> * | * - - - - * | <-- |7483:34|~52~3
LC58 -> * | * - - - - * | <-- |7483:34|~52~4
LC78 -> * | * - - - - - | <-- |7483:34|~52~5
LC65 -> * | * - - - - * | <-- |7483:34|~52~6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\ex1\wuxinkun.rpt
wuxinkun
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--- LC21 P2
| +- LC18 |7483:33|~29~1
| |
| | Other LABs fed by signals
| | that feed LAB 'B'
LC | | | A B C D E F | Logic cells that feed LAB 'B':
Pin
9 -> * * | - * * * * * | <-- A0
12 -> * * | * * * * * * | <-- A1
10 -> * * | * * * * * * | <-- A2
8 -> - * | - * * * * * | <-- A3
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