traffic.vho

vhdl实现的交通灯

	datad => state_control_a0_a_DATAD_driver,
	aclr => state_control_a0_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => state_control(0));

state_control_a475_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => state_control_a475_DATAB_driver);

state_control_a475_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => state_control_a475_DATAC_driver);

state_control_a475_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => state_control_a475_DATAD_driver);

state_control_a475 : cyclone_lcell
-- Equation(s):
-- state_control_a475_combout = Equal8_a71_combout & (temp(0) # p2_a62_combout)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "f0c0",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => state_control_a475_DATAB_driver,
	datac => state_control_a475_DATAC_driver,
	datad => state_control_a475_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => state_control_a475_combout);

state_control_a1_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => state_control_a1_a_CLK_driver);

state_control_a1_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(0),
	dataout => state_control_a1_a_DATAA_driver);

state_control_a1_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(1),
	dataout => state_control_a1_a_DATAB_driver);

state_control_a1_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control_a475_combout,
	dataout => state_control_a1_a_DATAD_driver);

state_control_a1_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => state_control_a1_a_ACLR_driver);

state_control_a1_a : cyclone_lcell
-- Equation(s):
-- state_control(1) = DFFEAS(state_control(1) $ (state_control(0) & (state_control_a475_combout)), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "66cc",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => state_control_a1_a_CLK_driver,
	dataa => state_control_a1_a_DATAA_driver,
	datab => state_control_a1_a_DATAB_driver,
	datad => state_control_a1_a_DATAD_driver,
	aclr => state_control_a1_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => state_control(1));

ss_a31_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(0),
	dataout => ss_a31_DATAA_driver);

ss_a31_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(1),
	dataout => ss_a31_DATAC_driver);

ss_a31_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => ss_a31_DATAD_driver);

ss_a31 : cyclone_lcell
-- Equation(s):
-- ss_a31_combout = state_control(0) & (!state_control(1) & hz_aregout)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0a00",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => ss_a31_DATAA_driver,
	datac => ss_a31_DATAC_driver,
	datad => ss_a31_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => ss_a31_combout);

Mux0_a6_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(0),
	dataout => Mux0_a6_DATAA_driver);

Mux0_a6_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(1),
	dataout => Mux0_a6_DATAC_driver);

Mux0_a6 : cyclone_lcell
-- Equation(s):
-- Mux0_a6_combout = state_control(0) # state_control(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "fafa",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => Mux0_a6_DATAA_driver,
	datac => Mux0_a6_DATAC_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux0_a6_combout);

ss_a32_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(1),
	dataout => ss_a32_DATAB_driver);

ss_a32_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(0),
	dataout => ss_a32_DATAC_driver);

ss_a32_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => ss_a32_DATAD_driver);

ss_a32 : cyclone_lcell
-- Equation(s):
-- ss_a32_combout = state_control(1) & state_control(0) & hz_aregout

-- pragma translate_off
GENERIC MAP (
	lut_mask => "c000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => ss_a32_DATAB_driver,
	datac => ss_a32_DATAC_driver,
	datad => ss_a32_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => ss_a32_combout);

Mux1_a25_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(1),
	dataout => Mux1_a25_DATAB_driver);

Mux1_a25_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(0),
	dataout => Mux1_a25_DATAC_driver);

Mux1_a25 : cyclone_lcell
-- Equation(s):
-- Mux1_a25_combout = state_control(1) & !state_control(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0c0c",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => Mux1_a25_DATAB_driver,
	datac => Mux1_a25_DATAC_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux1_a25_combout);

ss_a0_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(1),
	dataout => ss_a0_a_DATAIN_driver);

ss_a0_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => ss_a0_a_DATAIN_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ss(0));

ss_a1_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => ss_a31_combout,
	dataout => ss_a1_a_DATAIN_driver);

ss_a1_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => ss_a1_a_DATAIN_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ss(1));

ss_a2_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => ALT_INV_Mux0_a6_combout,
	dataout => ss_a2_a_DATAIN_driver);

ss_a2_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => ss_a2_a_DATAIN_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ss(2));

ss_a3_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => ALT_INV_state_control(1),
	dataout => ss_a3_a_DATAIN_driver);

ss_a3_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => ss_a3_a_DATAIN_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ss(3));

ss_a4_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => ss_a32_combout,
	dataout => ss_a4_a_DATAIN_driver);

ss_a4_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => ss_a4_a_DATAIN_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ss(4));

ss_a5_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Mux1_a25_combout,
	dataout => ss_a5_a_DATAIN_driver);

ss_a5_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => ss_a5_a_DATAIN_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ss(5));

time1_a0_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => ALT_INV_d1(0),
	dataout => time1_a0_a_DATAIN_driver);

time1_a0_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => time1_a0_a_DATAIN_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_time1(0));

time1_a1_a_DATAIN_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => ALT_INV_d1(1),
	dataout => time1_a1_a_DATAIN_driver);

time1_a1_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => time1_a1_a_DATAIN_driver,
	devclrn =>