traffic.vho

vhdl实现的交通灯

	ena => d1_a3_a_ENA_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d1(3));

p2_a62_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(1),
	dataout => p2_a62_DATAA_driver);

p2_a62_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(2),
	dataout => p2_a62_DATAB_driver);

p2_a62_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(0),
	dataout => p2_a62_DATAC_driver);

p2_a62_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(3),
	dataout => p2_a62_DATAD_driver);

p2_a62 : cyclone_lcell
-- Equation(s):
-- p2_a62_combout = d1(1) & !d1(2) & d1(0) & !d1(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0020",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => p2_a62_DATAA_driver,
	datab => p2_a62_DATAB_driver,
	datac => p2_a62_DATAC_driver,
	datad => p2_a62_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => p2_a62_combout);

d2_a0_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d2_a0_a_CLK_driver);

d2_a0_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(0),
	dataout => d2_a0_a_DATAC_driver);

d2_a0_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d2_a0_a_ACLR_driver);

d2_a0_a : cyclone_lcell
-- Equation(s):
-- d2(0) = DFFEAS(!d2(0), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0f0f",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d2_a0_a_CLK_driver,
	datac => d2_a0_a_DATAC_driver,
	aclr => d2_a0_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d2(0));

d2_a594_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => d2_a594_DATAB_driver);

d2_a594_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d2_a594_DATAC_driver);

d2_a594_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => d2_a594_DATAD_driver);

d2_a594 : cyclone_lcell
-- Equation(s):
-- d2_a594_combout = !temp(0) & Equal8_a71_combout & p2_a62_combout

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => d2_a594_DATAB_driver,
	datac => d2_a594_DATAC_driver,
	datad => d2_a594_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => d2_a594_combout);

d2_a1_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d2_a1_a_CLK_driver);

d2_a1_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(0),
	dataout => d2_a1_a_DATAA_driver);

d2_a1_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(1),
	dataout => d2_a1_a_DATAB_driver);

d2_a1_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d2_a1_a_DATAC_driver);

d2_a1_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2_a594_combout,
	dataout => d2_a1_a_DATAD_driver);

d2_a1_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d2_a1_a_ACLR_driver);

d2_a1_a : cyclone_lcell
-- Equation(s):
-- d2(1) = DFFEAS(d2_a594_combout # d2(1) $ (d2(0) & !Equal8_a71_combout), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "ffc6",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d2_a1_a_CLK_driver,
	dataa => d2_a1_a_DATAA_driver,
	datab => d2_a1_a_DATAB_driver,
	datac => d2_a1_a_DATAC_driver,
	datad => d2_a1_a_DATAD_driver,
	aclr => d2_a1_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d2(1));

d2_a597_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(0),
	dataout => d2_a597_DATAA_driver);

d2_a597_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(1),
	dataout => d2_a597_DATAB_driver);

d2_a597_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(2),
	dataout => d2_a597_DATAC_driver);

d2_a597_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(3),
	dataout => d2_a597_DATAD_driver);

d2_a597 : cyclone_lcell
-- Equation(s):
-- d2_a597_combout = d2(3) $ (d2(0) & !d2(1) & !d2(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "fd02",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => d2_a597_DATAA_driver,
	datab => d2_a597_DATAB_driver,
	datac => d2_a597_DATAC_driver,
	datad => d2_a597_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => d2_a597_combout);

d2_a3_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d2_a3_a_CLK_driver);

d2_a3_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => d2_a3_a_DATAA_driver);

d2_a3_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => d2_a3_a_DATAB_driver);

d2_a3_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d2_a3_a_DATAC_driver);

d2_a3_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2_a597_combout,
	dataout => d2_a3_a_DATAD_driver);

d2_a3_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d2_a3_a_ACLR_driver);

d2_a3_a : cyclone_lcell
-- Equation(s):
-- d2(3) = DFFEAS(d2_a597_combout # p2_a62_combout & !temp(0) & Equal8_a71_combout, GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "ff20",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d2_a3_a_CLK_driver,
	dataa => d2_a3_a_DATAA_driver,
	datab => d2_a3_a_DATAB_driver,
	datac => d2_a3_a_DATAC_driver,
	datad => d2_a3_a_DATAD_driver,
	aclr => d2_a3_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d2(3));

d2_a2_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d2_a2_a_CLK_driver);

d2_a2_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(2),
	dataout => d2_a2_a_DATAA_driver);

d2_a2_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(3),
	dataout => d2_a2_a_DATAB_driver);

d2_a2_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(1),
	dataout => d2_a2_a_DATAC_driver);

d2_a2_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(0),
	dataout => d2_a2_a_DATAD_driver);

d2_a2_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d2_a2_a_ACLR_driver);

d2_a2_a : cyclone_lcell
-- Equation(s):
-- d2(2) = DFFEAS(d2(2) & (d2(1) # !d2(0)) # !d2(2) & !d2(3) & !d2(1) & d2(0), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "a1aa",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d2_a2_a_CLK_driver,
	dataa => d2_a2_a_DATAA_driver,
	datab => d2_a2_a_DATAB_driver,
	datac => d2_a2_a_DATAC_driver,
	datad => d2_a2_a_DATAD_driver,
	aclr => d2_a2_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d2(2));

Equal8_a71_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(2),
	dataout => Equal8_a71_DATAA_driver);

Equal8_a71_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(3),
	dataout => Equal8_a71_DATAB_driver);

Equal8_a71_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(1),
	dataout => Equal8_a71_DATAC_driver);

Equal8_a71_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d2(0),
	dataout => Equal8_a71_DATAD_driver);

Equal8_a71 : cyclone_lcell
-- Equation(s):
-- Equal8_a71_combout = !d2(2) & d2(3) & !d2(1) & d2(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0400",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => Equal8_a71_DATAA_driver,
	datab => Equal8_a71_DATAB_driver,
	datac => Equal8_a71_DATAC_driver,
	datad => Equal8_a71_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Equal8_a71_combout);

temp_a0_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => temp_a0_a_CLK_driver);

temp_a0_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => temp_a0_a_DATAB_driver);

temp_a0_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => temp_a0_a_DATAC_driver);

temp_a0_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => temp_a0_a_DATAD_driver);

temp_a0_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => temp_a0_a_ACLR_driver);

temp_a0_a : cyclone_lcell
-- Equation(s):
-- temp(0) = DFFEAS(temp(0) & !Equal8_a71_combout # !temp(0) & Equal8_a71_combout & p2_a62_combout, GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3c0c",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => temp_a0_a_CLK_driver,
	datab => temp_a0_a_DATAB_driver,
	datac => temp_a0_a_DATAC_driver,
	datad => temp_a0_a_DATAD_driver,
	aclr => temp_a0_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => temp(0));

state_control_a0_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => state_control_a0_a_CLK_driver);

state_control_a0_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => state_control(0),
	dataout => state_control_a0_a_DATAA_driver);

state_control_a0_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => state_control_a0_a_DATAB_driver);

state_control_a0_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => state_control_a0_a_DATAC_driver);

state_control_a0_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => state_control_a0_a_DATAD_driver);

state_control_a0_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => state_control_a0_a_ACLR_driver);

state_control_a0_a : cyclone_lcell
-- Equation(s):
-- state_control(0) = DFFEAS(state_control(0) $ (Equal8_a71_combout & (temp(0) # p2_a62_combout)), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "5a6a",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => state_control_a0_a_CLK_driver,
	dataa => state_control_a0_a_DATAA_driver,
	datab => state_control_a0_a_DATAB_driver,
	datac => state_control_a0_a_DATAC_driver,